Jan. 18, 2010Wafer-Scale 3D Integration of InGaAs Image Sensors with Si Readout Circuits
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-μm pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
[Lincoln Laboratory, Massachusetts Institute of Technology]

Jan. 18, 2010A 4-Side Tileable Back Illuminated 3D-Integrated Mpixel CMOS Image Sensor
[MIT Lincoln Laboratory, Irvine Sensors, Forza Silicon]