NEW Filter our 316 articles by market or company:
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
[EDA360 Insider]
Video interview of David Desharnais (Cadence) by Jeff Wolf (SOI Industry Consortium)
[Chipestimate.tv]
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]
NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications.
[NXP]
How an SOI MEMS are built : MEMS first™ process
[SiTime]
A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]

Last post on February 03, 2012:
STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display
#18 - Fall/Winter 2011/12
SOI on the Roadmaps
(Courtesy of ARM, IBM, and Soitec, August 2007)
SOI provides significant PPA advantages over bulk CMOS for digital applications using standard EDA flows and physical IP.
SOI CMOS technical benefits compared to bulk CMOS:
| Higher performance | Lower power | Area savings | High reliability |
|---|---|---|---|
| Reduced junction capacitance translates into faster transistor ON/OFF switching speed | SOI circuit higher performance capability allows voltage (Vdd) reduction | Synthesis tool picks samller cell in SOI to achieve a given speed in digital design | Reduced susceptibility to electro-magnetic interference |
| Boost effect of floating body during transistions | Smaller cells needed to achieve the same performance | No wells, no taps, no latchup in SOI, enables denser layout | Reduced soft error rates (SER) |
| No reverse substrate bias effect in cells using stacked transistors | Reduced junction capacitance | SOI eDRAM provides high-density memory | SOI circuits are capable of withstanding higher temperatures (~300°C) |
• higher performance at the same power
• lower dynamic power for the same performance
Mobile devices, where:
• lower dynamic power reduces the overall operating power for graphic-intensive mobile applications;
• RF design can strongly benefit from SOI substrate isolation and passive component enhancement;
• application processors target higher performance in tighter power envelopes for the next digital mobile experience.
Consumer electronics and gaming, where:
• smaller form factors are key;
• better thermal management is required;
• performance gains can simplify system designs.
Embedded markets, where:
• the emphasis is on performance, size, power and reliability especially under challenging conditions as found in automotive, industrial, and medical markets.
Dataprocessing including graphics and storage, where:
• SOI is intended to enable higher system performance, more cache memory, and better power envelope management, leading to cheaper packaging solutions.
ARTICLE Intel Delays Finfets
[Electronics Weekly]
ARTICLE ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
ARTICLE White paper: Considerations for Bulk CMOS to FD-SOI Design Porting
[SOI Industry Consortium]
ARTICLE Workshop: Fully Depleted SOI - April 28, 2011 - Hsinchu, Taiwan
[SOI Industry Consortium]
PUBLICATION Planar FD-SOI CMOS: The Competitive Advantage Mobile Silicon Technology
[SOI Industry Consortium]
PRESENTATION Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips
[Horacio Mendez, Executive Director, SOI Industry Consortium]