SOI Applications
NEW Filter our 377 articles by market or company:
Updated: May 22, 2013
SOI Fundamentals
Bulk vs SOI FinFET
[SOI Industry Consortium]
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
NEW Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
DATE: FDSOI costs to match bulk by year end, says ST
[Tech Design Forum]
Design/IP
GlobalFoundries to Fab 28/20nm FD-SOI Chips for ST; ST Technology Open to Other GF Customers
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Analog/HV/RF
High Voltage and High Reliability Silicon-on-Insulator Power IC Technologies and Their Application to 750 V 4.5 A Micro-Inverter IC
[Japanese Journal of Applied Physics 51 (2012)]
Smart power saves power
ST’s newest SOI-based smart power technology delivers big reductions in power consumption in medical equipment, hybrid-electric-vehicle chargers and more.
[Advanced Substrate News]
Photonics
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
Photonics on the Move
SOI is at the heart of silicon photonics. Here’s an overview of past, present and future trends.
[Advanced Substrate News]
Power
NovaThor SmartPhone Chip on 28nm FD-SOI: ST-Ericsson Blogger Tells All; PC Mag Sees Light
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Sensors/MEMS
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News]
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
Last post on May 22, 2013 by Adele HARS:
More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP
#20 – Fall/Winter 2012/13
The Move to Fully-Depleted: Manufacturing, Economics, Design
- FD-SOI: ST/Chery interview; CMP's MPW runs; IBS on cost-savings
- FD & wafers: SEH & Soitec
- IBM's Fin-on-Oxide/FinFET
- SOI Consortium – FD-SOI & wafer capacity for mobile
Benefits of SOI
(Courtesy of ARM, IBM, and Soitec, August 2007)
SOI provides significant PPA advantages over bulk CMOS for digital applications using standard EDA flows and physical IP.
SOI CMOS technical benefits compared to bulk CMOS:
| Higher performance | Lower power | Area savings | High reliability |
|---|---|---|---|
| Reduced junction capacitance translates into faster transistor ON/OFF switching speed | SOI circuit higher performance capability allows voltage (Vdd) reduction | Synthesis tool picks samller cell in SOI to achieve a given speed in digital design | Reduced susceptibility to electro-magnetic interference |
| Boost effect of floating body during transistions | Smaller cells needed to achieve the same performance | No wells, no taps, no latchup in SOI, enables denser layout | Reduced soft error rates (SER) |
| No reverse substrate bias effect in cells using stacked transistors | Reduced junction capacitance | SOI eDRAM provides high-density memory | SOI circuits are capable of withstanding higher temperatures (~300°C) |
• higher performance at the same power
• lower dynamic power for the same performance
It's ideal for a broad set of applications
Mobile devices, where:
• lower dynamic power reduces the overall operating power for graphic-intensive mobile applications;
• RF design can strongly benefit from SOI substrate isolation and passive component enhancement;
• application processors target higher performance in tighter power envelopes for the next digital mobile experience.
Consumer electronics and gaming, where:
• smaller form factors are key;
• better thermal management is required;
• performance gains can simplify system designs.
Embedded markets, where:
• the emphasis is on performance, size, power and reliability especially under challenging conditions as found in automotive, industrial, and medical markets.
Dataprocessing including graphics and storage, where:
• SOI is intended to enable higher system performance, more cache memory, and better power envelope management, leading to cheaper packaging solutions.
Hot news
PRESENTATION Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
EVENT FD-SOI Workshop 2013 - June 15, 2013 - Kyoto, Japan
[SOI Industry Consortium]
PRESENTATION Symposium: Fully Depleted Transistors Technology - December 10, 2012 – San Francisco, CA
[SOI Industry Consortium]
WHITE PAPER White paper: Innovative wafers for energy-efficient CMOS technology
WHITE PAPER White paper: Economic impact of the technology choices at 28nm/20nm
ARTICLE DAC 2012: video interview of Horacio Mendez, Executive Director, SOI Industry Consortium
[EDACafe.com]
