(Animated presentation courtesy of IBM)

Concerns about soft error rate have recently received a lot of attention. This is primarily caused by the increased susceptibility of circuits due to smaller geometries, decreased voltages with smaller noise margin, and reduced stored charges. Traditionally, the reliability worries due to soft errors have been focused on the memory elements; however as geometries have reached 45nm and below, the probability of a single event upset in logic circuits is very real. Logic soft errors are particularly critical because such an event produces a catastrophic system failure.

Large efforts by major suppliers, such as described in 2008 ISSCC, are underway in an attempt to create and implement design techniques to correct soft errors in bulk. However, SOI has an intrinsically well documented 5X to 10X lower soft error rate than bulk. The oxide layer acts as a block for the track of electron-holes pairs to drift to the p-n junctions.

This presentation describes the physical mechanism responsible for the significant reduction of soft errors in SOI.