SOI Applications
NEW Filter our 377 articles by market or company:
Updated: May 22, 2013
SOI Fundamentals
Bulk vs SOI FinFET
[SOI Industry Consortium]
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
DATE: FDSOI costs to match bulk by year end, says ST
[Tech Design Forum]
Design/IP
GlobalFoundries to Fab 28/20nm FD-SOI Chips for ST; ST Technology Open to Other GF Customers
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Analog/HV/RF
High Voltage and High Reliability Silicon-on-Insulator Power IC Technologies and Their Application to 750 V 4.5 A Micro-Inverter IC
[Japanese Journal of Applied Physics 51 (2012)]
Smart power saves power
ST’s newest SOI-based smart power technology delivers big reductions in power consumption in medical equipment, hybrid-electric-vehicle chargers and more.
[Advanced Substrate News]
Photonics
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
Photonics on the Move
SOI is at the heart of silicon photonics. Here’s an overview of past, present and future trends.
[Advanced Substrate News]
Power
NovaThor SmartPhone Chip on 28nm FD-SOI: ST-Ericsson Blogger Tells All; PC Mag Sees Light
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Sensors/MEMS
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News]
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.
#20 – Fall/Winter 2012/13
The Move to Fully-Depleted: Manufacturing, Economics, Design
- FD-SOI: ST/Chery interview; CMP's MPW runs; IBS on cost-savings
- FD & wafers: SEH & Soitec
- IBM's Fin-on-Oxide/FinFET
- SOI Consortium – FD-SOI & wafer capacity for mobile
Mission
The SOI Industry Consortium is a group of leading companies from the electronics industry with the mission of accelerating silicon-on insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption.
- The SOI Industry Consortium strives to be the unifying voice of the SOI based industry.
- The organization's mission is to both enable the extensive use of SOI design and technology by removing economic and technical barriers and to accelerate innovation to further amplify the value to the end customer.
- The SOI Industry Consortium provides its members with a platform for meaningful global collaborations throughout the value chain.
Leading SOI Innovation into Broader Markets
Goals
Our goal is to enable the collaborative innovation required to:
- Explicitly state the SOI value and leverage the inherent advantages of SOI technology throughout the entire value chain and into end user products.
- Identify list of physical IP needed by market segments and facilitate IP and design validation to make it available on a competitive timeline.
- Accelerate the current technology / product roadmap for both high performance and low power consumer applications.
- Maximize financial returns by shortening time to market for the members.
Benefits
The SOI Industry Consortium provides to members a highly integrated bundle of complementary skills and knowledge that enable the industry to leverage SOI technology and design by:
- Sharing the effort to deploy SOI, thereby reducing the cost of adoption
- Offering easy access to resources, knowledge, expertise and deliverables
- Coordinating access to customer requirements and supply chain partners
- Shortening the learning curve, accelerating the Time To Market
- Providing clear roadmap and early access to technology that supports product development
- Increasing the global knowledge
- Influencing the growth and direction of the industry
- Enabling new markets
Hot news
PRESENTATION Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
EVENT FD-SOI Workshop 2013 - June 15, 2013 - Kyoto, Japan
[SOI Industry Consortium]
PRESENTATION Symposium: Fully Depleted Transistors Technology - December 10, 2012 – San Francisco, CA
[SOI Industry Consortium]
WHITE PAPER White paper: Innovative wafers for energy-efficient CMOS technology
WHITE PAPER White paper: Economic impact of the technology choices at 28nm/20nm
ARTICLE DAC 2012: video interview of Horacio Mendez, Executive Director, SOI Industry Consortium
[EDACafe.com]
