SOI Applications
NEW Filter our 316 articles by market or company:
SOI Fundamentals
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
[EDA360 Insider]
Design/IP
Video interview of David Desharnais (Cadence) by Jeff Wolf (SOI Industry Consortium)
[Chipestimate.tv]
Analog/HV/RF
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Photonics
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
Power
A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]
NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications.
[NXP]
Sensors/MEMS
How an SOI MEMS are built : MEMS first™ process
[SiTime]
A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
Last post on February 03, 2012:
STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display
#18 - Fall/Winter 2011/12
SOI on the Roadmaps
- FD-SOI: ST & 28nm SOCs; ARM & design porting
- Apps – NXP automotive sensors, AMD 32nm Bulldozer
- SOI Conference (IBM, Intel, Leti, GloFo, ST, ARM, Peregrine & more)
- SOI Consortium – FD-SOI whitepaper overview & excerpts
Mission
The SOI Industry Consortium is a group of leading companies from the electronics industry with the mission of accelerating silicon-on insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption.
- The SOI Industry Consortium strives to be the unifying voice of the SOI based industry.
- The organization's mission is to both enable the extensive use of SOI design and technology by removing economic and technical barriers and to accelerate innovation to further amplify the value to the end customer.
- The SOI Industry Consortium provides its members with a platform for meaningful global collaborations throughout the value chain.
Leading SOI Innovation into Broader Markets
Goals
Our goal is to enable the collaborative innovation required to:
- Explicitly state the SOI value and leverage the inherent advantages of SOI technology throughout the entire value chain and into end user products.
- Identify list of physical IP needed by market segments and facilitate IP and design validation to make it available on a competitive timeline.
- Accelerate the current technology / product roadmap for both high performance and low power consumer applications.
- Maximize financial returns by shortening time to market for the members.
Benefits
The SOI Industry Consortium provides to members a highly integrated bundle of complementary skills and knowledge that enable the industry to leverage SOI technology and design by:
- Sharing the effort to deploy SOI, thereby reducing the cost of adoption
- Offering easy access to resources, knowledge, expertise and deliverables
- Coordinating access to customer requirements and supply chain partners
- Shortening the learning curve, accelerating the Time To Market
- Providing clear roadmap and early access to technology that supports product development
- Increasing the global knowledge
- Influencing the growth and direction of the industry
- Enabling new markets
Hot news
ARTICLE Intel Delays Finfets
[Electronics Weekly]
ARTICLE ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
ARTICLE White paper: Considerations for Bulk CMOS to FD-SOI Design Porting
[SOI Industry Consortium]
ARTICLE Workshop: Fully Depleted SOI - April 28, 2011 - Hsinchu, Taiwan
[SOI Industry Consortium]
PUBLICATION Planar FD-SOI CMOS: The Competitive Advantage Mobile Silicon Technology
[SOI Industry Consortium]
PRESENTATION Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips
[Horacio Mendez, Executive Director, SOI Industry Consortium]
