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Updated: May 22, 2013
Bulk vs SOI FinFET
[SOI Industry Consortium]
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
DATE: FDSOI costs to match bulk by year end, says ST
[Tech Design Forum]
GlobalFoundries to Fab 28/20nm FD-SOI Chips for ST; ST Technology Open to Other GF Customers
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
High Voltage and High Reliability Silicon-on-Insulator Power IC Technologies and Their Application to 750 V 4.5 A Micro-Inverter IC
[Japanese Journal of Applied Physics 51 (2012)]
Smart power saves power
ST’s newest SOI-based smart power technology delivers big reductions in power consumption in medical equipment, hybrid-electric-vehicle chargers and more.
[Advanced Substrate News]
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
Photonics on the Move
SOI is at the heart of silicon photonics. Here’s an overview of past, present and future trends.
[Advanced Substrate News]
NovaThor SmartPhone Chip on 28nm FD-SOI: ST-Ericsson Blogger Tells All; PC Mag Sees Light
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News]
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.
#20 – Fall/Winter 2012/13
The Move to Fully-Depleted: Manufacturing, Economics, Design
Feb. 24, 2011Planar FD-SOI CMOS: The Competitive Advantage Mobile Silicon Technology
Only Planar Fully-Depleted SOI CMOS Technology will enable the optimal Power-Performance-Area-Cost and Time-to-Market balance you need for your next generation Mobile Product development.
[SOI Industry Consortium]
Oct. 14, 2008Join us! We're the force behind the solution
Collaborate: Chipmakers. Suppliers. Users. Enablers. Actively working together.
Innovate: Identifying the challenges. Finding the gaps. Building the solutions.
Accelerate: Getting the word out. Reaching broader markets. Leveraging the power of many.
Aug. 15, 2007Consider SOI technology - The right solution for more applications than you think !
Did you know that for a wide range of applications:
- SOI can help give you an edge anytime you have to balance power, performance and area.
- It can help simplify design and manufacturing, and increase reliability.
- Plus, there’s a very good chance you’ll find it significantly more cost-effective than bulk CMOS.
PRESENTATION Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
EVENT FD-SOI Workshop 2013 - June 15, 2013 - Kyoto, Japan
[SOI Industry Consortium]
PRESENTATION Symposium: Fully Depleted Transistors Technology - December 10, 2012 – San Francisco, CA
[SOI Industry Consortium]
WHITE PAPER White paper: Innovative wafers for energy-efficient CMOS technology
WHITE PAPER White paper: Economic impact of the technology choices at 28nm/20nm
ARTICLE DAC 2012: video interview of Horacio Mendez, Executive Director, SOI Industry Consortium
[EDACafe.com]