SOI Applications
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SOI Fundamentals
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
[EDA360 Insider]
Design/IP
Video interview of David Desharnais (Cadence) by Jeff Wolf (SOI Industry Consortium)
[Chipestimate.tv]
Analog/HV/RF
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Photonics
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
Power
A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]
NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications.
[NXP]
Sensors/MEMS
How an SOI MEMS are built : MEMS first™ process
[SiTime]
A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
Last post on February 03, 2012:
STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display
#18 - Fall/Winter 2011/12
SOI on the Roadmaps
- FD-SOI: ST & 28nm SOCs; ARM & design porting
- Apps – NXP automotive sensors, AMD 32nm Bulldozer
- SOI Conference (IBM, Intel, Leti, GloFo, ST, ARM, Peregrine & more)
- SOI Consortium – FD-SOI whitepaper overview & excerpts
3D integration
Sep. 1, 2010Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
May. 31, 2010Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
May. 17, 2010MIT Lincoln lab's 3D integration process and its application to integrate InP on SOI wafers
[MIT Lincoln Laboratory]
Jan. 18, 2010A 4-Side Tileable Back Illuminated 3D-Integrated Mpixel CMOS Image Sensor
[MIT Lincoln Laboratory, Irvine Sensors, Forza Silicon]
Jan. 18, 2010Wafer-Scale 3D Integration of InGaAs Image Sensors with Si Readout Circuits
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-μm pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
[Lincoln Laboratory, Massachusetts Institute of Technology]
Hot news
ARTICLE Intel Delays Finfets
[Electronics Weekly]
ARTICLE ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
ARTICLE White paper: Considerations for Bulk CMOS to FD-SOI Design Porting
[SOI Industry Consortium]
ARTICLE Workshop: Fully Depleted SOI - April 28, 2011 - Hsinchu, Taiwan
[SOI Industry Consortium]
PUBLICATION Planar FD-SOI CMOS: The Competitive Advantage Mobile Silicon Technology
[SOI Industry Consortium]
PRESENTATION Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips
[Horacio Mendez, Executive Director, SOI Industry Consortium]
