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Analog/High Voltage/RF

May. 25, 2010Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]

Feb. 16, 2010RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]

May. 27, 2009All of VTI Technologies’ MEMS products are based on SOI wafers
The company’s CMA 3000 multi-axis accelerometer is the “stride sensor chip” in the miCoach real-time training system launched by adidas and Samsung last year.
[Advanced Substrate News]

Jan. 1, 2009RFMD RF MEMS transmit/receive switch and an RF MEMS mode-switch for 3G multimode handsets
[RFMD]

Jul. 16, 2008Analog Circuit Design in SOI
IBM's Tony Bonaccio shows how analog designers reap the same SOI benefits as their confreres in the digital world.
[Advanced Substrate News]

May. 7, 2008FinFET technology for analog and RF circuits
FinFET technology presents a competitive alternative to planar CMOS as it features a better control of the short channel effects. This results in improved digital and analog performances. The radio-frequency (RF) behavior is however affected by a large level of parasitics. In this paper, we explain how technological options and device design affect the FinFET performance. In addition, the challenges and opportunities for both wideband modeling and the design of analog and RF circuits are identified and discussed.
B. Parvais, V. Subramanian, A. Mercha, M. Dehan, P. Wambacq, W. Sanssen, G. Groeseneken, S. Decoutere
[14th IEEE International Conference on Electronics, Circuits and Systems, 2007, pp.182-185]

Feb. 20, 2008High-voltage device integration simplifies design of Power-over-Ethernet powered devices
[Dataweek]

Feb. 3, 2008Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies
CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.
Wambacq, P.; Mercha, A.; Scheir, K.; Verbruggen, B.; Borremans, J.; De Heyn, V.; Thijs, S.; Linten, D.; Van der Plas, G.; Parvais, B.; Dehan, M.; Decoutere, S.; Soens, C.; Collaert, N.; Jurczak, M.
[ISSCC 2008. Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 2008]

Nov. 12, 2007The Potential of FinFETs for Analog and RF Circuit Applications
CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.
Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidy Subramanian, Nadine Collaert, Malgorzata Jurczak and Stefaan Decoutere
[IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 54, Issue 11, pp. 2541-2551]

Nov. 5, 2007ESD protection for sub-45 nm MugFET technology
From the design point of view, while such technology options may result in increased transistor performance, the ability to achieve sufficient product reliability is to be addressed. Among the industry accepted reliability requirements, electrostatic discharge (ESD) reliability assessment is the focus of this work.
M.I. Natarajan, S. Thijs, D. Tremouilles, D. Linten, N. Collaert, M. Jurczak, G. Groeseneken
[14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007, pp. 159-164]

Oct. 22, 2007Analysis of the FinFET parasitics for improved RF performances
FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are derived to improve the RF performance. For an optimized layout folding, experiments indicate 15% gain in f_T.
B. Parvais, M. Dehan, V. Subramanian, A. Mercha, K. Tamer San, M. Jurczak, G. Groeseneken, W. Sansen and S. Decoutere
[2007 IEEE International SOI Conference, pp. 37-38]

Oct. 1, 2007Analog Devices' ADL5387 wideband 50 MHz to 2 GHz demodulator
For high capacity broadband modem applications.
[Analog Devices]

Apr. 17, 2007Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective
Based on careful physical description, the effect of gate-length downscaling on the RF performance of double-gate fin field-effect transistors (finFETs) has been analyzed. Downscaling is beneficial to the device RF performance although the losses due to series parasitics increase. The source/drain series resistance in finFET largely limits the device RF performance, and the losses due to the gate resistance increase with reducing gate length. Double-gate finFETs have the potential to reach the RF International Technology Roadmap for Semiconductor targets in the few decananometer regime, but meeting the specification for gate length in the order of 10 nm may require further improvements.
Sebastien Nuttinck, Bertrand Parvais, Gilberto Curatola, Abdelkarim Mercha
[IEEE Transactions on Electron Devices, Vol. 54, Issue 2, pp. 279-283]

Apr. 6, 2006Tronics/ELAMedical
[Advanced Substrate News]

Apr. 18, 2005Soitec - SOI for RF & Low Power ICs
[Advanced Substrate News]

Apr. 10, 2005How SOI makes a difference in RF & low-power ICs
[Advanced Substrate News]

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