Design/IP

Jun. 14, 2012GlobalFoundries to Fab 28/20nm FD-SOI Chips for ST; ST Technology Open to Other GF Customers
[Advanced Substrate News]

Apr. 30, 2012Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]

Apr. 24, 2012ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond
STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights.
[Advanced Substrate News]

Apr. 23, 2012Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond
FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length.
[Advanced Substrate News]

Apr. 20, 2012Soitec: Wafer Roadmap for Fully Depleted Planar and 3D/FinFET
[Advanced Substrate News]

Apr. 6, 2012Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]

Dec. 6, 2011Bulk logic designs for mobile apps port directly to FD-SOI
[Advanced Substrate News]

Aug. 1, 2011Study Shows FD-SOI Most Cost-Effective Approach at 22nm
A new IC Knowledge report examines the costs of potential solutions for a foundry at 22nm.
[Advanced Substrate News]

Jul. 5, 2011New Wii U™ on SOI
Nintendo’s next high-profile, high-volume CPU will leverage IBM’s 45nm SOI for performance, power and eDRAM.
[Advanced Substrate News]

Jun. 1, 2011Get Smart
ST’s latest BCD shows how SOI yet again enables huge reductions in power consumption.
[Advanced Substrate News]

May. 27, 2011FD-SOI: A Quick Backgrounder
For those new to FD-SOI, here’s a short description of the basic principles.
[Advanced Substrate News]

May. 27, 20115th FD-SOI Workshop (Taiwan)
Following the April 2011 VLSI-TSA and VLSI-DAT conferences in Hsinchu, Taiwan, the SOI Consortium hosted the fifth in its series of FD-SOI Workshops.
[Advanced Substrate News]

May. 27, 2011Bulk to SOI Porting Analysis
One of the key projects currently underway within the SOI Consortium is to understand and provide guidance on the advantages and obstacles of porting SoC designs from Bulk to FD-SOI. This project represents a strategic opportunity to help drive the profile of FD SOI and participate in the emergence of this important technology.
[Advanced Substrate News]

May. 27, 2011FD-SOI update
Data indicates that fully-depleted (FD) SOI offers an ideal combination for achieving ultra-low-power, high-performance and cost-effective manufacturability. Companies in the SOI Consortium are working together on furthering the development and technology evaluations.
[Advanced Substrate News]

May. 25, 2011FD-SOI: The Substrates Are Ready
At the most recent SOI Consortium FD-SOI workshop, Soitec gave a presentation on FD-SOI substrate readiness. Here are some of the highlights.
[Advanced Substrate News]

May. 14, 2011FD-SOI: The Right Choice
[Advanced Substrate News]

May. 4, 2011ESD Protection for Advanced SOI
Deeply scaled PD- and FD-SOI require new approaches to ESD protection. Recent work from Stanford and GlobalFoundries on gate controlled FEDs shows great promise.
[Advanced Substrate News]

Apr. 22, 2011What Smart Stacking™ can do for you
Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more.
[Advanced Substrate News]

Apr. 6, 2011MEMS on SOI – Growing Fast and Faster
[Advanced Substrate News]

Mar. 11, 2011The SOI Papers at ISSCC 2011
[Advanced Substrate News]

Feb. 25, 2011Topple the Towers: Freescale’s SOI SoC in Alcatel-Lucent’s lightRadio

Feb. 18, 2011SOI: It’s Elementary, My Dear Watson
[Advanced Substrate News]

Feb. 10, 2011SOI Consortium’s phenomenal FD-SOI/ARM results
[Advanced Substrate News]

Jan. 24, 2011SOI Luminaries Shine in IEDM Awards
[Advanced Substrate News]

Jan. 13, 2011AMD’s New Fusion APU’s on 32nm SOI
[Advanced Substrate News]

Jan. 5, 20112011 & SOI: Doing It.
[Advanced Substrate News]

Dec. 21, 2010ARM Tunes SOI SPICE for PPA

Dec. 13, 2010Thinking Thin: NXP’s EZ-HV-SOI
[Advanced Substrate News]

Dec. 13, 2010Newest Drivers Reach New Levels of Integration
[Advanced Substrate News]

Dec. 13, 2010Let There Be (Better!) Light
SOI is a central pillar of NXP’s energy-efficient lighting strategy. In this exclusive ASN interview, Jacques Le Berre, the company’s director of marketing and business development for Lighting Solutions, explains why.
[Advanced Substrate News]

Dec. 13, 2010Driving Light
SOI is poised to take center stage in the impending lighting revolution, with companies like NXP leading the charge. Here’s why.
[Advanced Substrate News]

Dec. 8, 2010SOI Conference Short Course
[Advanced Substrate News]

Dec. 8, 2010What’s new: Design Clinics now online
[Advanced Substrate News]

Dec. 8, 2010The FD SOI workshop series: A Big Success
Now in their second year, these information-packed workshops are bringing in the key decision makers, and gathering ecosystem support.
[Advanced Substrate News]

Dec. 8, 2010Self-Heating Effect and Variability in Gate-All-Around (GAA) Silicon Nanowire Transistors (SNWT)
Researchers in academia have partnered with industry to increase understanding of critical issues in advanced non-classical CMOS devices.
[Advanced Substrate News]

Dec. 8, 2010FD SOI: Movers & Shakers at Tokyo Workshop
The third installment in the SOI Consortium’s ongoing FD SOI Workshop series, the Tokyo event was a major success.
[Advanced Substrate News]

Dec. 8, 2010The 2010 IEEE SOI Conference
For 35 years the IEEE/Electron Devices Society’s SOI Conference has been the premier meeting of engineers and scientists dedicated to current trends in SOI.
[Advanced Substrate News]

Dec. 8, 2010Right Timing
ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models.
[Advanced Substrate News]

Dec. 8, 2010Wafers for Fully Depleted SOI Devices: Ready for Volume
A technological tour-de-force, Soitec’s wafers for FD SOI meet all the requirements
[Advanced Substrate News]

Jul. 26, 2010In the pipeline
[Advanced Substrate News]

Jul. 26, 2010ARM/EETimes Virtual Conference
[Advanced Substrate News]

Jul. 26, 2010Jump Start SOI Training
[Advanced Substrate News]

Jul. 26, 2010The SOI IP Portal
[Advanced Substrate News]

Jul. 26, 2010Program Launch: Ready for SOI Technology
The goal is to build a visible, working IP ecosystem to support SOI adoption.
[Advanced Substrate News]

Jul. 26, 2010On the Leading Edge
Jean-Pierre COLLINGE reflects on why key advances in transistor research start on SOI.
[Advanced Substrate News]

Jul. 26, 2010Low Power Analog CMOS for Cardiac Pacemakers: Design Optimization in Bulk and SOI Technologies
[Advanced Substrate News]

Jul. 26, 2010To the Nanowire
SOI-based nanowire chips from nanosens can detect biochemical entities at the molecular level at room temperature.
[Advanced Substrate News]

Jul. 26, 2010Get the Picture
Hitachi's latch-up-free, SOI-based chips enable new generations of compact medical ultrasound systems.
[Advanced Substrate News]

Jul. 26, 2010Smart Sense
Denis FLANDRE describles how UCL researchers leverage SOI in a powerful, affordable sensor design.
[Advanced Substrate News]

Jul. 26, 2010In the Lab
Leti's healthcare research includes SOI-based sensors.
[Advanced Substrate News]

Jul. 26, 2010X-Ray Visionaries
Developed for use in high energy particle physics, applications for KEK’s new SOIPIX technology can also extend to medical imaging.
[Advanced Substrate News]

Jul. 26, 2010The Moment Is Now
Nobuyuki SUGII of Hitachi recounts why their thin-BOX SOI solution also benefits today's mainstream low-power nodes.
[Advanced Substrate News]

Jul. 26, 2010Conquering Convergence
Frederic BŒUF of STM and Claire FENOUILLET-BERANGER of Leti describe how their hybrid FD-SOI/bulk approach solves multi-media SoC challenges.
[Advanced Substrate News]

Jul. 26, 2010ETSOI Substrates: What We Need
Bruce DORIS of IBM explains the relationship between the device architecture and SOI wafer requirements.
[Advanced Substrate News]

Jul. 26, 2010Model Behavior
Olivier ROZEAU of CEA-Leti discusses SPICE-ready compact models for FD-SOI.
[Advanced Substrate News]

Jul. 26, 2010Using FD-SOI to Design Competitive Chips
Xavier CAUCHY of Soitec looks at why FD-SOI is interesting for competitive chip design.
[Advanced Substrate News]

Jul. 26, 2010Fully Depleted (FD) SOI for the Next Generation
FD-SOI: A Primer. What is it? What's it for? When will it hit?
[Advanced Substrate News]

Jul. 1, 2010Cissoid further extends its lines of SOI-based products for high-temperature environments with a DC-DC converter platform, fast drivers for power transistors, and power MOSFETs.
[Cissoid]

Jul. 1, 2010PhD Studentship: Design of VLSI Cellular Processor Arrays, UK
Sum 100nm bulk CMOS and Silicon on Insulator (SOI) technologies will be considered. The project involves international collaboration with partners in Finland and USA.Candidates should have a degree in Electronics, Computer Engineering, ...
[Scholarship Positions]

Jul. 1, 2010EDA Consolidation Continues
It too is expanding its product portfolio and launched a comprehensive silicon-on-insulator (SoI) Design Hub, a new Web portal that will help lower barriers to adoption of SoI technology by reducing initial start-up costs, reducing time ...
[Sramana Mitra on Strategy]

Jun. 18, 2010Video interview of David Desharnais (Cadence) by Jeff Wolf (SOI Industry Consortium)
[Chipestimate.tv]

Jun. 9, 2010Cadence Announces Comprehensive SOI Design Hub
[Cadence]

Mar. 24, 2010IBM, ARM and Cadence collaborate to provide chip and system designers access to key IP
[PC's Semiconductors Blog]

Mar. 23, 2010Ready for SOI IP Ecosystem Program
[by Jeff Wolf, SOI Industry Consortium]

Mar. 22, 2010ARM CTO warns of dark silicon
[Embedded.com]

Mar. 15, 2010Looking ahead to designing with ARM
[Embedded.com]

Mar. 8, 2010Designing high-temp electronics for auto and other apps
[by Pierre Delatte, Automotive DesignLine]

Mar. 8, 2010Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm
[by Gerard Boudon, IBM Microelectronics]

Feb. 16, 2010Soitec announces volume production of new generation of high-resistivity SOI substrates for cellular phone and Wi-Fi markets
[Soitec]

Feb. 2, 2010TowerJazz and Soitec sign agreement to offer backside illumination platform for high-end image sensors
[Soitec]

Jan. 22, 2010STMicroelectronics Introduces World’s Most Integrated High-Performance Ultrasound Pulse Controller
[STMicroelectronics]

Dec. 4, 2009The right choice for 22nm SRAM
Researchers at UC Berkeley, where the FinFET was originally developed, have found that a planar fully depleted SOI transistor structure on thin-BOX can offer adequate SRAM performance and yield at the 22nm node. By Tsu-Jae King Liu and Changhwan Shin, UC Berkeley.
[Advanced Substrate News]

Dec. 4, 2009“Foundry of the Year” for Tronics
EuroAsia Semiconductor magazine rewards growth in the downturn.
[Advanced Substrate News]

Dec. 4, 2009Driving SOI Cost Reductions
With cost savings leveraged across the board, prices are coming down significantly. By Dr. Jocelyne Wasselin, VP Marketing & Business Development, Soitec.
[Advanced Substrate News]

Dec. 4, 2009High volume, high yield production
Leading device manufacturers are leveraging the latest in-line inspection equipment for 45nm SOI-based devices. By William Shen, Ph.D., Senior Product Manager, KLA-Tencor Corporation.
[Advanced Substrate News]

Dec. 4, 2009Increased expectations, drastic reductions
A novel transistor design creates a new family of ultra-low power blocks – with consumption measured in sub-nanowatts. By Denis Flandre, Head of Microelectronics Lab, UC Louvain.
[Advanced Substrate News]

Dec. 4, 2009Understanding SRAM sense amps in SOI design
In those rare cases where designers need to eliminate the history effect in an SOI SRAM design, easily implementable solutions are at hand. By Nghia Phan, Distinguished Engineer, IBM Systems and Technology Group.
[Advanced Substrate News]

Dec. 4, 2009SOI’s seven ESD design advantages
A prolific author and leading ESD expert, Dr. Voldman explains why SOI is a great tool for tackling electrostatic discharge.
[Advanced Substrate News]

Dec. 4, 2009Implementing the 45nm SOI ARM11
The mobile app chip’s 40% power saving was achieved without any major rework in design methodology. By Roma Rudra, Staff Design Engineer, ARM.
[Advanced Substrate News]

Dec. 4, 2009Digital implementation with SOI: go with the float
Off-the-shelf solutions eliminate SOI design-time overhead. By Dhananjay K. Griyage, Senior R&D Engineer and Michael Jacobs, Senior Product Manager, Cadence Design Systems.
[Advanced Substrate News]

Dec. 1, 2009Soitec and CEA-Leti to join forces to speed commercial adoption of 3D integration
[Soitec]

Nov. 16, 2009SOI Digital Implementation & Electrical Signoff
By Michael Jacobs and Dhananjay Griyage
[Cadence Design Systems]

Nov. 16, 2009Circuit Design with Planar and Vertical FD-SOI Transistors
By Borivoje Nikolić and Tsu-Jae King Liu
[University of California, Berkeley]

Sep. 18, 2009IBM has developed a 32nm SOI prototype of the smallest, densest and fastest on-chip eDRAM
It uses four times less standby power and has up to a thousand times lower soft-error rate. The technology will be used by a wide range of ASIC and foundry clients, and as well as in IBM’s servers. An initial 32nm ARM library is available now, with 22nm development also underway. Details will be described at IEDM in December.
[IBM Press Room]

Sep. 14, 2009“De-myth-tifying” the SOI Floating body effect
By Bob Ulicki, Herb Reiter
[SOI Industry Consortium]

Jul. 30, 2009A Novel Device for Ultra-Low Power & More
A leading figure in the research world, Professor Woo and his team are taking an innovative approach to taming the power challenge. By Jason Woo, Professor, UCLA.
[Advanced Substrate News]

Jul. 30, 2009Interview of David Kress, director of Technical Marketing, Analog Devices: Innovation, Lower Leakage & Higher Performance
Analog Devices’ proprietary XF3 SOI SiGe complementary bipolar process enables them to address the trends toward reduced component cost, board area and power consumption — all while delivering unparalleled performance.
[Advanced Substrate News]

Jul. 30, 2009White Goods Get Greener
A new joint venture by LS and Infineon will leverage SOI-based power modules.
[Advanced Substrate News]

Jul. 30, 2009Low Power Design: Fast & Green
SOI helps create faster chips that consume less power. By Karen Bartleson, Sr. Director Community Marketing, Synopsys Inc.
[Advanced Substrate News]

Jul. 30, 2009IBM & SOI: Delivering on Customer Priorities
How IBM’s Cu-45HP ASIC leverages SOI for an overall lowering of power. By Dr. Raj Singh, Senior Technical Staff Member & Communications Architect, IBM Microelectronics Division.
[Advanced Substrate News]

Jul. 30, 2009Energy-Efficient SoC Design Can Make A Difference
ARM now offers a combination of low-power processors, SOI libraries and power management IP. By Remy Pottier, Head of SOI Marketing and Business Development, ARM.
[Advanced Substrate News]

Jul. 30, 2009Construction on GlobalFoundries’ Fab 2 in Saratoga County, New York, gets underway this summer
With full-scale manufacturing slated for 2012.
[Advanced Substrate News]

Jul. 28, 2009The MOSIS Service has expanded its relationship with IBM
The MOSIS Service, a leading provider of semiconductor fabrication solutions, has expanded its relationship with IBM to 45nm SOI for System-on-Chips (SOCs) and 180nm 7RF SOI for RF switches. This provides a low-cost route to prototyping and low-volume production.
[Mosis]

Jul. 27, 2009Cadence Validates ARM Optimized Libraries for 45nm SOI Process
[Cadence]

Jun. 22, 2009Roadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic
[UC Louvain]

Jun. 15, 2009Soitec’s 300mm ultra-thin SOI (UTSOI) wafer platform is qualified and ready for FD-SOI applications at 22nm and beyond
The extremely thin top-layer silicon (<20nm) is manufactured to a thickness uniformity tolerance of ±5 Å (angstroms) in high volume with high yields.
[Soitec]

May. 27, 2009Jazz Semiconductor, a foundry leader in Analog-Intensive Mixed-Signal (AIMS) solutions
It includes support for SOI-based designs in its new Direct Multiproject Wafer (MPW) shuttle program, offering quick and low-cost prototyping for commercial and military/defense customers.
[Jazz]

May. 27, 2009For pure-play MEMS leader Silex, SOI offers clear advantages
[Advanced Substrate News]

May. 27, 2009GlobalFoundries: high-performance 45nm SOI technology
The Dresden cluster, the company’s current primary manufacturing facility, will be re-named Fab 1, with Module 1 initially focused on production of high-performance 45nm SOI technology. Jim Doran has been named senior vice president and general manager of Fab 1. It will be in the IBM technology development alliance for SOI.
[Advanced Substrate News]

May. 27, 2009High-performance 45nm SOI
[Advanced Substrate News]

Apr. 8, 2009The PSP Model in RF CMOS Design
[Fujitsu]

Feb. 23, 2009SOI Circuit Design Overview
By Nghia Phan, Distinguished Engineer
[IBM Systems and Technology Group]

Feb. 4, 2009A new suite of efficient power supply products including GreenChip PFC and SR controllers
Based on its 3rd generation of high-voltage SOI (EZ-HV) processes developed specially to handle power, analog and digital devices on a single die, NXP has announced: A new suite of efficient power supply products including GreenChip PFC and SR controllers to replace energy inefficient diode rectification circuits with cost efficient IC implementation in computing, consumer and industrial power supplies. With over 400 million products in the market, the GreenChip family makes it easier and more cost-effective for power supply manufacturers to comply with energy efficiency specifications such as 80PLUS® and ENERGY STAR®.
[NXP]

Feb. 2, 2009Design methodology of FinFET devices that meet IC-Level HBM ESD targets
A new design methodology for FinFET devices is presented which takes into account all complex dependencies on both layout and process parameters of the electrical ESD device parameters of FinFET gated diodes and NMOS FinFET devices in both parasitic bipolar and active MOS operation mode. This methodology allows optimization towards a given ESD target (area consumption, leakage current, parasitic capacitance,...) while fulfilling several imposed design constraints. KiloVolt HBM levels in FinFETs are demonstrated meeting the full IC-level ESD requirements.
S. Thijs, C. Russ, D. Trémouilles, D. Linten, M. Scholz, M. Jurczak, N. Collaert, R. Rooyackers, M. Sawada, T. Nakaei, T. Hasebe, C. Duvvury, H. Gossner and G. Groeseneken
[EOS/ESD 2008. 30th Electrical Overstress/Electrostatic Discharge Symposium]

Dec. 3, 200845nm SOI
The Foundry Offering. The IP. The Collaboration. With recent announcements from IBM and ARM, it’s all here.
[Advanced Substrate News]

Dec. 3, 2008e2v’s new dual-core integrated 90nm SOI processors
The PC8641D and PC8572, are extended-reliability versions of Freescale’s MPC8641D and MPC8572. They target massive data processing embedded applications, including radars, flight computers and graphic displays.
[Advanced Substrate News]

Dec. 3, 2008Freescale’s new MPC8536E SOI-based PowerQUICC III
Freescale’s new MPC8536E SOI-based PowerQUICC III is a 1.5 GHz SoC for applications requiring energy-efficient, fast processing of rich media content.
[Advanced Substrate News]

Nov. 24, 2008Ultra-scaled Z-RAM cell
Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.
By S. Okhonin, M. Nagoga, C.-W. Lee, J.-P. Colinge, A. Afzalian, R. Yan, N. Dehdashti Akhavan, W. Xiong, V. Sverdlov, S. Selberherr, C. Mazure
[Proceedings IEEE International SOI Conference, pp. 157-158, 2008]

Nov. 21, 2008Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities
This paper presents an extensive experimental study of the effective mobility in the long-channel undoped triple-gate FinFETs. The mobility behavior in FinFETs is studied as compared with that in quasi-planar very wide fin FETs made on the same wafers and as a function of the fin width. Devices with two types of the gate dielectrics are investigated. New insights about the carrier transport in triple-gate FinFETs are obtained using a careful analysis of the results for various fin widths. In particular, it is shown that the model treating the triple-gate FinFET in terms of the (100) top and (110) lateral channels is not perfectly accurate for describing the transport properties in real FinFETs with relatively narrow fins; at low and moderate inversion charge densities, this is due to different inversion carrier distributions (and, thus, nonidentical scattering rates for various fin widths), and at high charge densities, it is presumably due to fin rounding which results in ambiguous crystallographic orientation, different from the postulated (100) and (110).
Tamara Rudenko, Valeriya Kilchytska, Nadine Collaert, Malgorzata Jurczak, Alexey Nazarov and Denis Flandre
[IEEE Transactions on Electron Devices, Vol. 55, Issue 12, pp. 3532-3541]

Nov. 21, 2008Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications
Electrostatic discharge performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing parameters. Both N- and P-type MOS FinFET devices are characterized in bipolar operation mode as a function of layout parameters such as gate length and fin width. The impact of well implants, selective epitaxial growth, and strain is studied.
S. Thijs, D. Tremouilles, C. Russ, A. Griffoni, N. Collaert, R. Rooyackers, D. Linten, M. Scholz, C. Duvvury, H. Gossner, M. Jurczak, G. Groeseneken
[IEEE Transactions on Electron Devices, Vol. 55, Issue 12, pp. 3507-3516]

Nov. 10, 2008ARM Announces Industry’s First Silicon-On-Insulator Physical IP Library For IBM’s New 45nm SOI Foundry
[ARM]

Oct. 30, 2008Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs
The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs.
By Chi-Woo Lee, Dimitri Lederer, Aryan Afzalian, Ran Yan, Nima Dehdashti, Weize Xiong, Jean-Pierre Colinge
[Solid-State Electronics, Vol. 52, No. 11, pp. 1815–1820, 2008]

Oct. 25, 2008Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs
The impact of strain-engineering on the low frequency of n-channel tri-gate FinFETs fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused on the study of nFinFETs with a standard structure and with strain-engineered channel structures, using either global or local straining techniques, or a combination of both. A carrier number fluctuation dominant flicker noise has been observed for all devices. Whereas no clear correlation between the applied strain techniques and the 1/f noise level has been found, an unusual noise spectral density was observed for the devices with selective epitaxial grown (SEG) source and drain regions. This unusual noise behaviour has been investigated for different fin widths (0.15 μm up to 3 μm) and different temperature conditions (150 K up to 300 K). An empirical model is proposed in order to explain this unusual noise behaviour. Moreover, two Lorentzians attributed to defects in the depletion region of the silicon fin were observed, and energy level and cross-section of these defects were estimated.
W. Guo, B. Cretu, J.-M. Routoure, R. Carin, E. Simoen, A. Mercha, N. Collaert, S. Put, C. Claeys
[Solid-State Electronics, Vol. 52, Issue 12, December 2008, pp. 1889-1894 ]

Oct. 24, 2008A 10-Bit Current-Steering FinFET D/A Converter
In this paper we present the first complex mixed-signal FinFET circuit (>1500 devices). Design and implementation aspects as well as measurement results of a 10-bit current- steering D/A converter are shown. The achieved performance proves the ability of recent FinEET technology to realize competitive mixed-signal circuits with large device count and wide range of device dimensions. Moreover the promising matching and analog behavior of FinFETs enables reduced circuit area compared to planar designs.
M. Fulde, F. Kuttner, K. v. Arnim, B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, M. Becherer, D. Schmitt-Landsiedel and G. Knoblinger
[2008 IEEE International SOI Conference, pp. 95-96]

Oct. 24, 2008Comparison of scaled floating body RAM architectures
In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
N. Collaert, M. Rosmeulen, M. Rakowskia, R. Rooyackers, L. Witters, A. Veloso, J. Van Houdt and M. Jurczak
[2008 IEEE International SOI Conference Proceedings, pp. 35-36]

Sep. 23, 2008High-Frequency Noise Performance of 60-nm Gate-Length FinFETs
In this paper, the first-ever published investigation on radio-frequency (RF) noise performance of FinFETs is reported. The impact of the geometrical dimensions of FinFETs on RF noise parameters such as the channel length, the fin width, as well as the fin number is analyzed. A minimum noise figure of 1.35 dB is obtained with an associated available gain of 13.5 dB at 10 GHz for Vdd = 0.5 V. This result is quite encouraging to bring solutions for future low-power RF systems.
Jean-Pierre Raskin, Guillaume Pailloncy, Dimitri Lederer, François Danneville, Gilles Dambrine, Stefaan Decoutere, Abdelkarim Mercha and Bertrand Parvais
[IEEE Transactions on Electron Devices, Vol. 55, Issue 10, pp. 2718-2727]

Aug. 5, 2008Capping-Metal Gate Integration Technology for multiple-VT CMOS in MuGFETs
We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.
A. Veloso, L. Witters, M. Demand, I. Ferain1, N. J. Son2, B. Kaczer, Ph. J. Roussel, C. Adelmann, S. Brus, O. Richard, H. Bender, T. Conard, R. Vos, R. Rooyackers, S. Van Elshocht, N. Collaert, K. De Meyer1, S. Biesemans, and M. Jurczak
[2008 Symposium on VLSI Technology, pp. 14-15]

Jul. 16, 2008IBM’s Tony Bonaccio shows how analog designers reap the same SOI benefits as their confreres in the digital world
[Advanced Substrate News]

Jul. 16, 2008Mentor’s tools keep SOI transparent and robust, explains Michael White
[Advanced Substrate News]

Jul. 16, 2008Kevin Kranen of Synopsys describes how designers can “have it all” with SOI
[Advanced Substrate News]

Jul. 16, 2008Remy Pottier looks behind the SOI doors ARM is opening
[Advanced Substrate News]

Jul. 15, 2008Perspective of RF design in future planar and FinFET CMOS
Scaling of CMOS transistors beyond 45 nm requires architectural redesign of the devices. FinFETs are proposed to recover the reduced channel control. This work evaluates the perspective of RF design in planar bulk vs. FinFET SOI for (sub-)45 nm CMOS on a key RF circuit: a low-noise amplifier (LNA). The planar and FinFET devices with channel lengths down to 40 nm are compared in both wideband and narrowband designs up to 14 GHz to illustrate the RF and ESD protection performance perspective. Planar devices push the RF performance. FinFETs lag somewhat behind, but show promising RF performance.
J. Borremans, B. Parvais, M. Dehan, S. Thijs, P. Wambacq, A. Mercha, M. Kuijk, G. Carchon, S. Decoutere
[2008 IEEE Radio Frequency Integrated Circuits Symposium]

Jul. 1, 2008Cissoid has announced its CHT-74 Logic Family for Extreme Temperatures
The products are optimized for high-temperature and high-reliability applications, with a very large temperature range (-55°C to 225°C). Target markets include Oil & Gas, Aeronautics, Space and Automotive.
[Cissoid]

May. 14, 2008Layman’s brief guide to FD vs PD SOI
[Advanced Substrate News]

May. 12, 2008Design Methodology for FinFET GG-NMOS ESD Protection Devices
In this paper, a design methodology is presented which takes into account all complex dependencies of the electrical ESD device parameters of a Grounded-Gate-NMOS FinFET device on its layout parameters. This allows finding the minimum area solution which fulfills all imposed design constraints.
S. Thijs, C. Russ, D. Trémouilles, D. Linten, M. Scholz, M. Jurczak, N. Collaert, R. Rooyackers, C. Duvvury, H. Gossner and G. Groeseneken
[IMEC, International ESD Workshop, 2008]

May. 12, 2008Challenges and solutions for ESD protection in advanced logic and RF CMOS technologies
In this paper we review the challenges and possible solutions for the ESD protection of the new CMOS-based technologies. In the first part of the paper we will discuss the implications when classical scaling is maintained, and we will show that the ESD design window will be drastically decreased. Traditional ESD protection solutions, such as the dual-diode approach, will not be an option anymore and new techniques need to be introduced. In the second part we review some of the recent results that have been obtained using Multiple gate technologies. We demonstrate that reasonableintrinsic ESD performance can be obtained, but achieving this desired ESD-robustness is found to be critically dependent on various design and process parameters. As a result the design of ESD protection for FinFET technology appears to bea challenging task for the future. In the third part, we show that new solutions for the ESD protection of RF CMOS circuits can be obtained. These solutions can either be based onESD-RF co- design solutions or in a ‘plug-and-play’ approach. As an example a novel T-diode protection approach will be demonstrated for the protection of an LNA for UWB- applications, achieving HBM protection upto5 kV.
[IMEC, International ESD Workshop 2008]

Feb. 26, 2008Mentor Graphics advanced lithography tools are now IBM qualified for production of 45nm Cells
Accelerated with an SOI-based Cell/B.E. cluster from Mercury Computer Systems.
[Mentor Graphics]

Feb. 19, 2008Advanced SOI Technology for RF Applications Short Course
For RF applications, SOI offers key advantages over bulk. It provides the ability to meet very low voltage and low noise applications, allows for improvement of passive devices and improves integration capabilities to reduce cost. This short course details the considerations for RF design with SOI.
By Christine Raynaud
[CEA-LETI / STMicroelectronics]

Feb. 3, 2008Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies
CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.
Wambacq, P.; Mercha, A.; Scheir, K.; Verbruggen, B.; Borremans, J.; De Heyn, V.; Thijs, S.; Linten, D.; Van der Plas, G.; Parvais, B.; Dehan, M.; Decoutere, S.; Soens, C.; Collaert, N.; Jurczak, M.
[ISSCC 2008. Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 2008]

Jan. 23, 2008Comparison Between Analog Performance of Standard and Strained Triple-Gate nFinFETs
This work shows a comparison between the analog performance of standard and strained Si (sSOI) n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length have similar analog properties whereas the increase of the channel length degrades the Early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain.
M. A. Pavanello, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert and C. Claeys
[Proceedings EUROSOI Conference, 2008]

Jan. 23, 2008DC and RF characteristics of FinFET over a wide temperature range
DC and RF characteristics of n-type FinFET transistor over a wide temperature range, from 77 to 473K, are presented for the first time. We experimentally demonstrate that the impact of temperature on the main analog and RF factors of merit of FinFETs is similar to what it can be observed for classical deep submicron single gate MOSFETs.
J. C. Tinoco, B. Parvais, A. Mercha, S. Decoutere and J.-P. Raskin
[Proceedings EUROSOI Conference, 2008]

Dec. 11, 2007Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices
Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for Ultra-Low-Power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-VGS self-biasing. ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13-µm technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-VT devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.
David Bol, Renaud Ambroise, Denis Flandre and Jean-Didier Legat
[14th IEEE International Conference on Electronics, Circuits and Systems, pp. 1404-1407, 2007]

Dec. 1, 2007A Smarter Approach to Multi-Core: Freescale’s Next-Generation Communications Platform
See p. 4 for role of SOI.
[Freescale]

Nov. 19, 2007Low-power design animates panel in Taiwan
By Ron Wilson, Executive Editor, EDN
[EDN]

Nov. 12, 2007The Potential of FinFETs for Analog and RF Circuit Applications
CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.
Piet Wambacq, Bob Verbruggen, Karen Scheir, Jonathan Borremans, Morin Dehan, Dimitri Linten, Vincent De Heyn, Geert Van der Plas, Abdelkarim Mercha, Bertrand Parvais, Cedric Gustin, Vaidy Subramanian, Nadine Collaert, Malgorzata Jurczak and Stefaan Decoutere
[IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 54, Issue 11, pp. 2541-2551]

Nov. 5, 2007Analytical Extraction of Small and Large Signal Models for FinFET Varactors
In this work we report on the small and large signal behaviour of advanced nMOS varactors fabricated in FinFET technology. This is the first paper showing large signal network analyzer (LSNA) measurements performed on FinFET varactors. These nonlinear measurements are modeled with a lookup table based model that is constructed using an accurate multi-bias small signal equivalent circuit. The validity of the extracted small and large signal models is verified through the very good agreement between measurements and simulations.
Giovanni Crupi, Dominique M. M.-P. Schreurs, Morin Dehan, Dongping Xiao, Alina Caddemi, Abdelkarim Mercha and Stefaan Decoutere
[Solid-State Electronics, Vol. 52, Issue 5, pp. 704-710 ]

Nov. 1, 2007Scaling the Challenge of Memory at 45nm and Below
By Jeff Lewis, VP Marketing, Innovative Silicon Inc.
[Chip Design Magazine]

Oct. 31, 2007RFMD: integration of PA functions on one chip
[Advanced Substrate News]

Oct. 31, 2007Steve Longoria/7RF SOI technology for mobile phone designers
[Advanced Substrate News]

Oct. 31, 2007ASN 8 - The Launching of the SOI Industry Consortium
[Advanced Substrate News]

Oct. 22, 2007Analysis of the FinFET parasitics for improved RF performances
FinFET architecture results in high level of parasitics that offset the performance gain that can be achieved through gate length scaling. In this work, we investigate technological solutions both at the process integration and layout levels to alleviate these limitations. Layout guidelines are derived to improve the RF performance. For an optimized layout folding, experiments indicate 15% gain in fT.
B. Parvais, M. Dehan, V. Subramanian, A. Mercha, K. Tamer San, M. Jurczak, G. Groeseneken, W. Sansen and S. Decoutere
[2007 IEEE International SOI Conference, pp. 37-38]

Oct. 9, 2007Jazz Semiconductor 0.18-micron Silicon Radio platform allows complete radio integration
Complete integration of the radio in a wireless device on a single piece of silicon integrating the transceiver, antenna switch, power amplifier (PA) and controllers.
[Jazz Semiconductor]

Oct. 8, 2007A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM
This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.
K. von Arnim, E. Augendre, C. Pacha, T. Schulz, K. T. San, F. Bauer, A. Nackaerts, R. Rooyackers, T. Vandeweyer, B. Degroote, N. Collaert, A. Dixit, R. Singanamalla, W. Xiong, A. Marshall, C. R. Cleavelin, K. Schrüfer and M. Jurczak3
[2007 IEEE Symposium on VLSI Technology, pp. 106-107]

Sep. 24, 2007Freescale's MPC8610 integrated host processor
Helps robots see and navigate in 3D space, enables touch screen kiosks to recognize voices and facial features, and allows cockpit controls to display images with outstanding resolution.
[Freescale]

Aug. 23, 2007Quantum-Wire Effects in Trigate SOI MOSFETs
Trigate SOI transistors have been modeled using the Poisson and Schrödinger equations. In devices with a large enough cross section, inversion channels form at the Si/SiO₂ interfaces, but in devices with a small section, volume inversion is clearly visible. A transition between a one-dimensional density of states to a two-dimensional density of states is observed when the height of the fin is increased. Current oscillations are experimentally observed when the gate voltage is increased. These are due to a quantum-wire effect in which electron mobility is affected by intersubband scattering.
By J.P. Colinge
[Solid-State Electronics, Vol. 51-9, pp. 1153-1160, 2007]

Jul. 1, 2007The Future of Connected Mobile Computing
Choice of manufacturing partner enables choice of process technology. Because silicon-on-insulator (SOI) enables higher performance and lower power than CMOS, it is the process of choice for all gaming platforms, satellite chips, ultra-low power circuits for watches and so on.
ARM has worked closely with foundry partner UMC to migrate 65nm CMOS to 65nm SOI (L65SOI). This is the first open foundry and IP offering for worldwide availability of 65nm SOI process technology. The solution comprises ARM's portfolio of standard cell library, I/O library and SRAM compiler, and UMC's manufacturing capability.
[Synopsys Insight]

May. 25, 2007Low temperature noise spectroscopy of 0.1 µm partially depleted silicon on insulator metal-oxide-semiconductor field effect transistors
The variations of the low frequency noise versus temperature have been used to characterize the traps at the Si/SiO2 interface and in the depletion layer of partially depleted silicon on insulator metal-oxide-semiconductor field effect transistors obtained from recent 0.1 µm processes. For this technology, it is shown that 1/f noise and Lorentzians do not have the same physical origin. Moreover, an additional implantation, which is performed to control the short-channel effects, is shown to increase trap densities in the depletion layer and at the Si/SiO2 interface.
I. Lartigau, J. M. Routoure, W. Guo, B. Cretu, R. Carin, A. Mercha, C. Claeys, E. Simoen
[Journal of Applied Physics, Vol. 101, Issue 10, 2007]

May. 11, 2007Mike Muller, ARM CTO on SOI for ASICs
[Advanced Substrate News]

May. 1, 2007Honeywell's SOI-based, 150nm rad-hard chip: HX5000
The world’s first 12-million gate ASIC specifically designed for radiation-tolerant and radiation-hardened applications.
[Honeywell]

May. 1, 2007Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables
The Fin field effect transistor (FinFET) is a multiple gate structure, which is recently emerging as a leading structure to continue the scaling of CMOS technology into the nanometer regime. This promising multiple gate structure has not only the advantage of reducing short channel effects but also of being compatible with the conventional planar CMOS technology. To our knowledge, this is the first letter addressing the nonlinear FinFET model validated by large signal network analyzer measurements. Here, we present a nonlinear FinFET model which is based on lookup tables. The accuracy of the developed model is completely and successfully verified through the comparison with nonlinear FinFET measurements.
Giovanni Crupi, Dominique M. M.-P. Schreurs, Dongping Xiao, Alina Caddemi, Bertrand Parvais, Abdelkarim Mercha, Stefaan Decoutere
[Microwave and Wireless Components Letters, IEEE, Vol. 17, Issue 5, pp. 361-363]

Apr. 5, 2007Accurate and reliable optical CD of MuGFET down to 10 nm
As device critical dimensions (CD) decrease, they approach the limits of standard metrology techniques and measuring features smaller than 20 nm represents a serious challenge. Within the framework of the 32 nm program at IMEC, a reliable and accurate approach to small feature metrology is required. We describe here a methodology aimed at measuring features down to 10nm by means of scatterometry. The results are compared to calibrated CDSEM measurements [1]. The active fins of a Multi Gate Field Effect Transistors (MuGFET) was measured across wafer and across batch. Scribe to cell correlation, wafer fingerprint, 3D profile, oxide thickness were also investigated. In particular, 3D profile information was compared to TEM. Our approach produced very consistent results for all measurement techniques (scatterometry, CDSEM and TEM) and it is now fully integrated in the IMEC production line to monitor the MuGFET platform.
P. Leray, G. F. Lorusso, S. Cheng, N. Collaert, M. Jurczak, S. Shirke
[Metrology, Inspection, and Process Control for Microlithography XXI, Proceedings of SPIE, Vol. 6518, 65183B]

Apr. 2, 2007A Two-Dimensional Model for Interface Coupling in Triple-Gate Transistors
The influence of the fin width on substrate-to-gate coupling in long-channel silicon-on-insulator triple-gate transistors is investigated. A complementary analysis, taking into account both the "front coupling" (variation of the front-channel threshold voltage VT1, as a function of the substrate bias VG2) and "back coupling" (variation of the back-channel threshold voltage VT2) as a function of the front-gate bias VG1) characteristics has been carried out. It is shown that the back coupling, as opposed to the front coupling, is highly sensitive to the fin width in narrow-channel devices and can even be used in fin width extraction. Simple analytical 2-D models for the body potential, VT1, and VT2 have been developed to clarify the experimental data, showing in particular the gradual control of the back interface potential by the lateral gates in narrow fins. The model stands as a 2-D generalization of the Lim and Fossum's well-known 1-D interface coupling model.
by K. Akarvardar, A. Mercha, S. Cristoloveanu, P. Gentil, E. Simoen, V. Subramanian, C. Claeys
[IEEE Transactions on Electron Devices, Vol. 54, Issue 4, pp. 767-775]

Mar. 27, 2007Impact of fin width on digital and analog performances of n-FinFETs
This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs (I–V, C–V and 1/f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.
V. Subramanian, A. Mercha, B. Parvais, J. Loo, C. Gustin, M. Dehan, N. Collaert, M. Jurczak, G. Groeseneken, W. Sansen and S. Decoutere
[Solid-State Electronics Volume 51, Issue 4, April 2007, Pages 551-559]

Mar. 5, 2007Characterization, modeling, and optimization of FinFET MOS varactors
For the first time, nMOS varactors fabricated in FinFET technology were characterized and modeled at microwave frequency. The RF analysis is carried out as a function of the fin width. It is shown that the fin width has nearly no impact on the tuning range of the device, but on the quality factor (Q). Best Q's are obtained for wide fin devices, mainly due to the reduction of the series resistances, and a higher intrinsic conductance.
Dehan M., Parvais B., Subramanian V., Gustin C., Loo J., Mercha A., Decoutere S.
[2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems]

Mar. 1, 2007Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode
A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode. The biasing of MOS transistors in very weak inversion, with negative gate-to-source voltages, results in a static current that lays orders of magnitude below that of conventional cross-coupled CMOS inverters. Based on our device, a 7-transistors SRAM cell is presented. Modeling, simulation and experimental characterization of the main properties of this cell are reported for a 0.13 mum partially-depleted SOI CMOS process. The feasibility of ultra-low leakage memory circuits is demonstrated experimentally by the design of a 256 times 1 bits SRAM column.
David Levacq, Vincent Dessard and Denis Flandre
[IEEE Journal of Solid-State Circuits, Vol. 42, Issue 3, March 2007]

Feb. 28, 2007MSC8144 quad-core DSP
[Freescale]

Jan. 30, 2007Low-frequency noise in silicon-on-insulator devices and technologies
An overview is given on the low-frequency (LF) noise of silicon-on-insulator (SOI) devices and technologies. In the first two parts, noise mechanisms specific for SOI are discussed, namely, the front–back-gate coupling in fully-depleted MOSFETs and the Lorentzian noise overshoot in floating-body operating transistors. In the next part, the impact of the technology (SOI substrate, gate stack processing, isolation module, ...) on the LF noise is described.
E. Simoen, A. Mercha, C. Claeys and N. Lukyanchikova
[Solid-State Electronics, Volume 51, Issue 1, January 2007, Pages 16-37 ]

Jan. 29, 2007Advanced CMOS device technologies for 45 nm node and below
We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG) candidates for scaled CMOS technologies are fully silicided (FUSI) gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT) are reported (17 ps at VDD=1.1 V and 20 pA/μm Ioff), meeting the ITRS 45 nm node requirement for low-power (LP) CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress) or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.
A. Veloso, T. Hoffmann, A. Lauwers, H. Yu, S. Severi, E. Augendre, S. Kubicek, P. Verheyen, N. Collaert, P. Absil, M. Jurczak and S. Biesemans
[Science and Technology of Advanced Materials Volume 8, Issue 3, April 2007, Pages 214-218]

Jan. 23, 2007Device design guidelines for nano-scale MuGFETs
The short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as DIBL, subthreshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. This number ranges from 2 for a double-gate device to 4 in a gate-all-around transistor. The equivalent gate number can be used in general equations to predict the absence or presence of short-channel effects. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.
By Chi-Woo Lee, Se-Re-Na Yun, Chong-Gun Yu, Jong-Tae Park, J.P. Colinge
[Solid-State Electronics 51-3, pp. 505-510, 2007]

Jan. 18, 2007Eight SOI advantages every designer should exploit
by Pierre Fazan, CTO and VP of engineering, Innovative Silicon Inc.
[Electronic Design]

Dec. 6, 2006Micralyne’s new platform makes robust, reliable SOI-MEMS faster, better, cheaper
[Advanced Substrate News]

Dec. 6, 2006Hitachi – why SOI for mu
[Advanced Substrate News]

Dec. 6, 2006Hitachi’s mu-chip for RFID
[Advanced Substrate News]

Dec. 6, 2006ARM moves in to SOI
[Advanced Substrate News]

Nov. 22, 2006High-temperature performance of state-of-the-art triple-gate transistors
High-temperature performance of state-of-the-art n-channel triple-gate transistors with 15 nm fin-width, 60 nm fin-height, undoped body, high-k gate dielectric and metal gate is reported. The degradation of the on-current, transconductance and subthreshold swing, the shift in threshold voltage, the increase in gate/drain leakages and off-current with the temperature are analyzed up to 200 °C. The comparison of short- and long-channel devices and the overall excellent performance at high temperature are outlined.
K. Akarvardar, A. Mercha, E. Simoen, V. Subramanian, C. Claeys, P. Gentil, S. Cristoloveanu
[Microelectronics Reliability Volume 47, Issue 12, December 2007, Pages 2065-2069]

Oct. 16, 2006Atmel's new high-voltage SMARTIS™ technology
[Atmel]

Jul. 11, 2006Cissoid: design for rugged environments
[Advanced Substrate News]

Jul. 11, 2006Honeywell’s SOI EDA tools partners
[Advanced Substrate News]

Jul. 11, 2006Honeywell: SOI history & benefits
Read more: Honeywell, Silicon On Insulator Technology
[Advanced Substrate News]

Jul. 11, 2006AMD & SOI: Winning with Performance/Watt/Dollar
Interview of Nick Kepler, AMD
[Advanced Substrate News]

Jun. 1, 2006Strained SOI (sSOI)
[Freescale]

Apr. 6, 2006Michael Gruver (IBM) gives his perspective on foundry customers and custom SOI design
[Advanced Substrate News]

Apr. 6, 2006Michael Gruver on custom SOI design
[Advanced Substrate News]

Jul. 11, 2005Brief History of SOI at IBM
[Advanced Substrate News]

May. 23, 2005Ultra-Low Power Flip-Flops for MTCMOS Circuits
This paper deals with new MTCMOS flip-flop architectures with high speed performance in active mode and ultra-low power dissipation in sleep mode. The use of new ultra-low leakage latch structure allows us to memorize the flip-flop state even during sleep mode and to strongly reduce the leakage in comparison with previous solutions.
David Levacq, Vincent Dessard, Denis Flandre
[IEEE International Symposium on Circuits and Systems, pp. 4681-4684, 2005]

Apr. 10, 2005How SOI makes a difference in RF & low-power ICs
[Advanced Substrate News]

Mar. 30, 2005Cell design services
[IBM]