Process technology

Jun. 23, 2010SOI Scalability
A more mainstream technology that has been around a while, Silicon-on-Insulator (SOI), is also an attractive option for very high performance ICs such as...
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]

Jun. 15, 2010Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
Time-dependent electrostatic field-induced second-harmonic (TD-EFISH) generation is used to probe optically excited hot carrier injection (HCI) from silicon-on-insulator (SOI) films as thin as 2 nm into both native oxide and buried oxide (BOX), without device fabrication. The two HCI processes induce TD-EFISH signals of opposite sign, at different rates, whereby they are distinguished straightforwardly. HCI at the SOI/BOX interface is dominated by two-photon injection into HF defect induced traps created during SOI thinning. The results demonstrate that SHG can noninvasively and quantitatively characterize HCI, a key determinant of SOI device reliability.
by Ming Lei, J. Price and M. C. Downer
[Applied Physics Letters, Vol. 96, Issue 24]

Jun. 3, 2010Reducing Polarization Dependent Loss of Silicon-on-Insulator Fiber to Chip Grating Couplers
For many telecommunication applications, low Polarization Dependent Loss (PDL) operation is mandatory. On the silicon-on-insulator photonic wire platform this can be achieved using polarization diversity configurations. However, as we show here, when using two dimensional grating couplers for near vertical fiber input and output, the low PDL bandwidth is limited. We propose and demonstrate the use of a π phase shifter in one of the arms of the polarization diversity circuit to effectively reduce PDL (0:15 dB PDL is shown) and increase the low PDL bandwidth.
by Robert Halir, Diedrick Vermeulen, and Günter Roelkens
[Universiteit Gent]

May. 24, 2010SOI Digital Technology Roadmap
by Horacio Mendez, SOI Industry Consortium
[Soi Industry Consortium]

May. 24, 2010Ultrafast optical switching based on nonlinear polarization rotation in silicon waveguides
We experimentally realize ultrafast all-optical switching in the 1.5-μm spectral region using cross-phase modulation inside a 5-mm long silicon waveguide. Modulation depths of up to 90% and switching window durations ~1 ps are achieved using 500-fs pump pulses with energies below 10 pJ.
by Jonathan Y. Lee, Lianghong Yin, Govind P. Agrawal and Philippe M. Fauchet
[Optics Express, Vol. 18, Issue 11, pp. 11514-11523]

May. 23, 2010Mid-infrared wavelength conversion in silicon waveguides using ultracompact telecom-band-derived pump source
by Sanja Zlatanovic, Jung S. Park, Slaven Moro, Jose M. Chavez Boggio, Ivan B. Divliansky, Nikola Alic, Shayan Mookherjea & Stojan Radic
[Nature Photonics]

May. 20, 2010An integrated optic ethanol vapor sensor based on a silicon-on-insulator microring resonator coated with a porous ZnO film
Optical structures fabricated on silicon-on-insulator technology provide a convenient platform for the implementation of highly compact, versatile and low cost devices. In this work, we demonstrate the promise of this technology for integrated low power and low cost optical gas sensing. A room temperature ethanol vapor sensor is demonstrated using a ZnO nanoparticle film as a coating on an SOI micro-ring resonator of 5 µm in radius. The local coating on the ring resonators is prepared from colloidal suspensions of ZnO nanoparticles of around 3 nm diameter. The porous nature of the coating provides a large surface area for gas adsorption. The ZnO refractive index change upon vapor adsorption shifts the microring resonance through evanescent field interaction. Ethanol vapor concentrations down to 100 ppm are detected with this sensing configuration and a detection limit below 25 ppm is estimated.
by Nebiyu A. Yebo, Petra Lommens, Zeger Hens and Roel Baets
[Optics Express, Vol. 18, Issue 11, pp. 11859-11866]

May. 15, 2010Saturation of the Raman amplification by self-phase modulation in silicon nanowaveguides
[Cornell University]

May. 1, 2010Temperature Effects on Silicon-on-Insulator (SOI) Racetrack Resonators: A Coupled Analytic and 2-D Finite Difference Approach
This paper presents a detailed analysis of racetrack resonators on silicon on insulator substrates. Both the temperature effects and the particularities of silicon nanophotonics are considered throughout the approach. This paper provides a detailed description of the numerical modeling and its application to different designs, while providing several charts and fitting equations. The results presented in this paper can be applied to three major applications: Thermo-optical tuning of optical resonators, thermo-optical modulator and wide range/high sensitivity temperature sensors. While quantifying the temperature effects, this paper also provides useful answers on how critical the temperature parameter is in the optical cavity behaviour.
Nicolas Rouger, Lukas Chrostowski, and Raha Vafaei
[Journal of Lightwave Technology, Vol. 28, Issue 9, pp. 1380-1391]

Mar. 1, 2010Tyndall claims first junctionless transistor
[Semiconductor Today]

Dec. 1, 2009Presentation: Silicon results of ARM core 1176 in SOI – A 40% power reduction
[by Remy Pottier, Jonathan Tong, Chris Hawkins, Roma Kundu and Jean-Luc Pelloie, ARM]

Sep. 16, 2009Building an SOI IP/EDA Infrastructure
[Cadence]

Aug. 6, 2009Localized Heating on Silicon Field Effect Transistors: Device Fabrication and Temperature Measurements in Fluid
We demonstrate electrically addressable localized heating in fluid at the dielectric surface of silicon-on-insulator field-effect transistors via radio-frequency Joule heating of mobile ions in the Debye layer. Measurement of fluid temperatures in close vicinity to surfaces poses a challenge due to the localized nature of the temperature profile. To address this, we developed a localized thermometry technique based on the fluorescence decay rate of covalently attached fluorophores to extract the temperature within 2 nm of any oxide surface. We demonstrate precise spatial control of voltage dependent temperature profiles on the transistor surfaces. Our results introduce a new dimension to present sensing systems by enabling dual purpose silicon transistor-heaters that serve both as field effect sensors as well as temperature controllers that could perform localized bio-chemical reactions in Lab on Chip applications.
by Oguz H. Elibol, Bobby Reddy, Jr, Pradeep R. Nair, Brian Dorvel, Felice Butler, Zahab Ahsan, Donald E. Bergstrom, Muhammad A. Alam and Rashid Bashir
[Lab Chip., Vol. 9, Issue 19, pp. 2789–2795]

Feb. 27, 2009First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling
Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.
Merelle, T. Curatola, G. Nackaerts, A. Collaert, N. van Dal, M.J.H. Doornbos, G. Doorn, T.S. Christie, P. Vellianitis, G. Duriez, B. Duffy, R. Pawlak, B.J. Voogt, F.C. Rooyackers, R. Witters, L. Jurczak, M. Lander, R.J.P.
[IEEE International Electron Devices Meeting 2008, pp. 1-4]

Feb. 6, 2009Junctionless multigate field-effect transistor
This paper describes a metal-oxide-semiconductor (MOS) transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.
Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, and Jean-Pierre Colinge
[Applied Physics Letters, Vol. 94, pp. 053511:1-2: 2009]

Feb. 2, 2009Electrostatic Discharge Effects in Fully Depleted SOI MOSFETs with Ultra-Thin Gate Oxide and Different Strain-Inducing Techniques
The ESD sensitivity of 65-nm fully depleted SOI MOSFETs (with thin silicon body) used as output buffer devices is studied. A detailed electrical investigation is carried out in order to classify the observed failure modes and mechanisms. We propose a new failure criterion that allows us to univocally identify the device failure. Finally, we analyze the impact of device geometry and strain engineering on the ESD sensitivity.
Alessio Griffoni, Augusto Tazzoli, Simone Gerardin, Eddy Simoen, Cor Claeys, and Gaudenzio Meneghesso
[30th Electrical Overstress/Electrostatic Discharge Symposium, 2008, pp. 59-66]

Jan. 25, 2009Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs
As MuGFETs are promising contenders for the end of the silicon Roadmap, their high-temperature behaviour needs to be addressed. In this work we investigate the variations of the subthreshold slope (SS) of double-gate devices and MuGFETs with intrinsic doping as a function of the temperature and fin width. Focus is placed on the superlinear behaviour of SS occurring above a certain temperature threshold. Numerical simulations are performed using Comsol Multiphysics™ and a 1D analytical model is developed. The model, which includes the effect of film and gate oxide thickness, is shown to accurately fit the numerical data. A new definition for the subthreshold slope under high-temperature operation is proposed. The high-temperature subthreshold slope degradation is shown to increase with fin width.
Jean-Pierre Colinge, Dimitri Lederer, Aryan Afzalian, Ran Yan, Chi-Woo Lee, Nima Dehdashti Akhavan
[Microelectronic Engineering, Vol. 86, Issue 10, pp. 2067-2071, 2009]

Jan. 19, 2009Microdose and Breakdown Effects Induced by Heavy Ions on Sub 32-nm Triple-Gate SOI FETs
We studied the permanent effects of heavy-ion strikes on decananometer triple-gate SOI devices. We highlighted the role of the geometry and the three-dimensional architecture in the response to heavy ions. Heavy-ion strikes in state-of-the-art Triple-Gate FETs may have measurable permanent effects, due to microdose in the buried oxide, breakdown of the gate oxide, or interface state generation in the side oxide/body interface. This last effect is particularly interesting since it is related to the verticality of multigate transistors.
Griffoni, A.; Gerardin, S.; Meneghesso, G.; Paccagnella, A.; Simoen, E.; Put, S.; Claeys, C.
[IEEE Transactions on Nuclear Science, Vol. 55, Issue 6, pp. 3182-3188 ]

Jan. 1, 2009Junctionless MuGFETs
This paper describes the simulation of the electrical characteristics of a new transistor concept called “Junctionless MuGFET”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical property than classical inversion-mode devices with S&D PN junctions.
Chi-Woo Lee, Aryan Afzalian, Ran Yan, Nima Dehdashti, J. P. Colinge
[Proceedings EUROSOI Conference, 2009]

Jan. 1, 2009Quantization effects in capacitance behaviour of nanoscale Si MuGFETs
An unusual bump in the gate capacitance characteristics of Si nanoscale MuGFETs is presented and explained here through 3D NEGF quantum simulations. As higher order subbands are populated when the gate voltage is increased, the channel moves closer to the surface. This increases the slope in the Id-Vg and creates the bump in the Cg(Vg) curve as the centroid of the charge moves closer to the Si/SiO2 interface and the capacitance is increased.
A. Afzalian, C.-W. Lee, R. Yan, N. Dehdashti, I. Ferrain, J.-P. Colinge
[Proceedings EUROSOI Conference, 2009]

Nov. 21, 2008Drain Breakdown Voltage in MuGFETs: Influence of Physical Parameters
This paper analyzes the drain breakdown voltage of multigate MOSFETs and the influence of parameters such as doping concentration, fin width, and gate length. The good electrostatic control of the active area by the multigate structure improves the drain breakdown voltage, which increases as the fin width is decreased. Increasing the channel doping concentration improves the drain breakdown voltage as well.
Chi-Woo Lee, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Weize Xiong, Jean-Pierre Colinge
[IEEE Transactions on Electron Devices, Vol. 55, no. 12, pp. 3503-3506, 2008]

Nov. 18, 2008Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization
Scaling the fin width in fully-depleted FinFETs can improve short channel effect control, but may be accompanied by a on-state drive current degradation. Ion implantation is a leading candidate as the means to introduce dopants into the silicon, but is often accompanied by amorphization when highly doped source-drain regions are formed. Thin-body silicon recrystallization after amorphization is not as straight-forward as bulk silicon. Crystalline integrity is worse as the fin width is scaled, thereby reducing dopant activation and increasing access resistance. In this work we demonstrate that non-amorphizing implant approaches can overcome drive degradation down to 10 nm wide fins in pMOS FinFETs.
Duffy, R. van Dal, M.J.H. Pawlak, B.J. Collaert, N. Witters, L. Rooyackers, R. Kaiser, M. Weemaes, R. Jurczak, M. Lander, R.
[38th European Solid-State Device Research Conference 2008, pp. 334-337]

Nov. 18, 2008Influence of Gate Underlap in AM and IM MuGFETs
The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode (AM) devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode (IM) FETs.
Chi-Woo Lee, Aryan Afzalian, Ran Yan, Nima Dehdashti, Weize Xiong, Jean-Pierre Colinge
[Proceedings of European Solid-State Device Research Conference (ESSDERC), pp. 238-241, 2008]

Nov. 18, 2008Metal gate thickness optimization for MuGFET performance improvement
In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization of MuGFETs and the physical analysis of their gate stacks, we show that the thickness of the TiN metal gate affects the nature of its reaction with the gate dielectric. This, in return, results into threshold voltage (VT) and gate inversion thickness (Tinv) modifications which can explain performance enhancement in n-FETs without any performance loss in p-FETs.
Ferain, I. Collaert, N. O'Sullivan, B. Conard, T. Popovici, M. Van Elshocht, S. Swerts, J. Jurczak, M. De Meyer, K.
[38th European Solid-State Device Research Conference 2008, pp. 202-205]

Nov. 18, 2008N-type VT tuning by Te ion implantation in moly-based metal gates with high-k dielectric for fully depleted devices
In the framework of fully depleted devices, we report up to 150 mV VT tuning towards the Si conduction band by implantation of Te into molybdenum capped with TiN, the dielectric being HfO2. Moderate post implant anneal seems to have no effect on the VT shift while high temperature anneal is needed to shift the EWF significantly. The temperature applied to the devices during the entire process is therefore crucial for driving the implanted species towards the Mo/high-k interface, where they can modify the interface dipole and hence modify the effective workfunction. Hence, high temperature standard pike anneal is a very interesting option. The effective workfunction shifts linearly with the dose. Moreover, the higher the implant energy, the larger the effect of the dose on the effective workfunction. Up to 10 keV, the device integrity is preserved after ion implantation. At higher energies, implanted ions penetrate into the high-k, which leads to Dit and subthreshold slope degradation. However, there is no evidence of counterdoping in this later case and gate leakage is hardly increased.
Petry, J. Boccardi, G. Xiong, K. Muller, M. Hooker, J. Singanamalla, R. Collaert, N. DeMeyer, K.
[38th European Solid-State Device Research Conference 2008, pp. 286-289]

Nov. 3, 2008Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth
This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance.
N. Collaert, R. Rooyackers, A. Hikavyy, A. Dixit, F. Leys, P. Verheyen, R. Loo, M. Jurczak, S. Biesemans
[Thin Solid Films, Vol. 517, Issue 1, pp. 101-104 ]

Oct. 30, 2008Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs
The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs.
By Chi-Woo Lee, Dimitri Lederer, Aryan Afzalian, Ran Yan, Nima Dehdashti, Weize Xiong, Jean-Pierre Colinge
[Solid-State Electronics, Vol. 52, No. 11, pp. 1815–1820, 2008]

Oct. 25, 2008Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs
The impact of strain-engineering on the low frequency of n-channel tri-gate FinFETs fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused on the study of nFinFETs with a standard structure and with strain-engineered channel structures, using either global or local straining techniques, or a combination of both. A carrier number fluctuation dominant flicker noise has been observed for all devices. Whereas no clear correlation between the applied strain techniques and the 1/f noise level has been found, an unusual noise spectral density was observed for the devices with selective epitaxial grown (SEG) source and drain regions. This unusual noise behaviour has been investigated for different fin widths (0.15 μm up to 3 μm) and different temperature conditions (150 K up to 300 K). An empirical model is proposed in order to explain this unusual noise behaviour. Moreover, two Lorentzians attributed to defects in the depletion region of the silicon fin were observed, and energy level and cross-section of these defects were estimated.
W. Guo, B. Cretu, J.-M. Routoure, R. Carin, E. Simoen, A. Mercha, N. Collaert, S. Put, C. Claeys
[Solid-State Electronics, Vol. 52, Issue 12, December 2008, pp. 1889-1894 ]

Oct. 24, 2008Comparison of scaled floating body RAM architectures
In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
N. Collaert, M. Rosmeulen, M. Rakowskia, R. Rooyackers, L. Witters, A. Veloso, J. Van Houdt and M. Jurczak
[2008 IEEE International SOI Conference Proceedings, pp. 35-36]

Oct. 24, 2008Influence of temperature on the operation of strained triple-gate FinFETs
In this work, the influence of the temperature variation, in the range of 200K up to 380K, on the performance of biaxially strained FinFETs with high-kappa dielectrics (HfO2), TiN metal gate and undoped body is investigated. It is demonstrated that narrow FinFETs present slightly smaller improvement at lower temperatures on the maximum transconductance (and hence mobility) and transconductance-to-drain current ratio than narrower ones. On the other hand, the subthreshold slope of narrow FinFETs is better than for narrow ones at any temperatue. The temperature reduction slightly reduces the gain of long-channel FinFETs in about 3 dB whereas the fin width increase from 20 nm to 870 nm degrades the gain by 13 dB at any temperature.
Pavanello, M.A. Martino, J.A. Simoen, E. Rooyackers, R. Collaert, N. Claeys, C.
[IEEE International SOI Conference 2008, pp. 55-56]

Sep. 26, 2008Accumulation-mode and inversion-mode triple-gate MOSFETs
This work analyzes the performance of very narrow triple-gate SOI MOSFETs on the basis of experimental and 3D simulation data. Short channel effects (SCEs) are quite reduced in those devices due to the good electrostatic control by the surrounding gate and the high Lg/Wfin ratio. The experimental data indicate that SCEs of accumulation-mode (AM) triple gate devices are comparable to those observed in inversion-mode (IM) devices down to a gate length of 50 nm. This makes AM triple gate (or more generally, multi-gate) MOSFETs interesting devices for digital applications.
R.Yan, A.Afzalian, C.-W. Lee, N.Dehdashti Akhavan, W.Xiong, J.-P. Colinge
[Proceedings of China-Ireland International Conference on Information and Communication Technologies (CIICT 2008), pp. 627-630, Sept. 2008]

Sep. 23, 2008High-Frequency Noise Performance of 60-nm Gate-Length FinFETs
In this paper, the first-ever published investigation on radio-frequency (RF) noise performance of FinFETs is reported. The impact of the geometrical dimensions of FinFETs on RF noise parameters such as the channel length, the fin width, as well as the fin number is analyzed. A minimum noise figure of 1.35 dB is obtained with an associated available gain of 13.5 dB at 10 GHz for Vdd = 0.5 V. This result is quite encouraging to bring solutions for future low-power RF systems.
Jean-Pierre Raskin, Guillaume Pailloncy, Dimitri Lederer, François Danneville, Gilles Dambrine, Stefaan Decoutere, Abdelkarim Mercha and Bertrand Parvais
[IEEE Transactions on Electron Devices, Vol. 55, Issue 10, pp. 2718-2727]

Sep. 18, 2008Innovative device architectures for Nanoscale CMOS
Nadine Collaert, IMEC
[4th Sinano-Nanosil Workshop 2008]

Sep. 1, 2008Influence of Fin Width on the Intrinsic Voltage Gain of Standard and Strained Triple-Gate nFinFETs
This work studies the influence of the fin width on the intrinsic voltage gain of standard and strained Si (sSOI) n-type triple-gate FinFETs with high-k dielectrics and metal gate. It is demonstrated that independent of the fin width the application of strain improves the device transconductance. On the other hand, the device output conductance shows a high dependence on the fin width in strained FinFETs with respect to standard ones. The output conductance degrades if narrow fins are used and improves for wide fins. Narrow strained FinFETs show a degradation of the Early voltage compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.
M. A. Pavanello, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert and C. Claeys
[ECS Transactions, Vol. 14, Issue 1, pp. 253-261]

Sep. 1, 2008Multi-gate devices for the 32nm technology node and beyond
Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on, planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.
N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L.-S. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B.J. Pawlak, R. Rooyackers, T. Schulz, K.T. San, N.J. Son, M.J.H. Van Dal, P. Verheyen, K. von Arnim, L. Witters, K. De Meyer, S. Biesemans and M. Jurczak
[Solid-State Electronics, Vol. 52, Issue 9, pp. 1291-1296]

Jul. 9, 2008Reliability issues in MuGFET nanodevices
In this paper we review some recent results on reliability of MuGFET nanodevices with different gate stacks, including polycrystalline-Si/SiON as well as deposited metal gate/high-k stacks. In the first part we show how we can get information on the interface quality of the sidewall and top interface of the devices, by using an adapted charge pumping technique on gated diode structures. Then we compare the TDDB behavior of MuGFET and planar devices and we will show that if adequate processing is used, the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown for different gate voltages and temperatures. Next we discuss the Bias Temperature Instability (BTI) behavior of MuGFET CMOS devices. Novel interface passivation techniques as well as the impact of different dielectric nitridation techniques on BTI are discussed, showing similar BTI dependence on Nitrogen incorporated in MuGFET dielectrics as in planar devices. Finally we also discuss the ESD performance of MuGFET devices and we demonstrate that reasonable intrinsic ESD performance can be obtained, but achieving this desired ESD-robustness is found to be critically dependent on various design and process parameters. As a result the design of ESD protection for FinFET technology appears to be a challenging task for the future.
G. Groeseneken, F. Crupi, A. Shickova, S. Thijs, D. Linten, B. Kaczer, N. Collaert, M. Jurczak
[IEEE International Reliability Physics Symposium, 2008, pp. 52-60]

Jun. 23, 2008Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations
In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔVTH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of VTH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.
Ran Yan, Danny Lynch, Thibault Cayron, Dimitri Lederer, Aryan Afzalian, Chi-Woo Lee, Nima Dehdashti, J.P. Colinge
[Solid-State Electronics, Vol. 52, No. 12, pp. 1872-1876, 2008]

Jun. 17, 2008Intel explores floating-body cells on SOI
[EE Times]

Jun. 17, 2008Methodology for Flatband Voltage Measurement in Fully Depleted Floating-Body FinFETs
Among the novel methods for flatband voltage (Vfb) measurement, we demonstrate that a gate-leakage-based technique is the most suitable for measuring Vfb in floating-body MOSFETs with ultrathin gate dielectrics. Starting from carrier separation experiments on planar MOSFETs, we show the universality of the gate conduction mechanism dependence on band alignment for both n- and p-FETs. We demonstrate that metrics based on the gate leakage (either its valence-band electron-tunneling component or its first-order derivative) reflect this dependence and allow equivalent-oxide-thickness-independent Vfb quantification. This dependence is also valid for high-k and capped gate dielectrics, whereas their gate conduction mechanism is dominated by direct tunneling. To illustrate, we extract gate-leakage-derivative-based metrics and measure Vfb of TaN and TiN gate electrodes in multiple-fin FETs integrated on silicon-on-insulator.
Ferain, I. Pantisano, L. O'Sullivan, B.J. Singanamalla, R. Collaert, N. Jurczak, M. De Meyer, K.
[IEEE Transactions on Electron Devices, Vol. 55, Issue 7, pp. 1657-1663]

Jun. 15, 2008MultiGate SOI MOSFETs: Accumulation-Mode vs. Enhancement-Mode
The performances of accumulation-mode and inversion-mode Multigate FETs are compared. Both simulation and experimental data are presented. Accumulation-mode devices have a higher current drive and less process variability than inversion-mode FETs.
A. Afzalian, D. Lederer, C.W. Lee, R. Yan, W. Xiong, C. Rinn Cleavelin, JP Colinge
[IEEE 2008 Silicon Nanoelectronics Workshop, P1-6, June 15-16, Honolulu, USA, 2008]

May. 23, 2008Conformal Doping of FINFET's: A Fabrication and Metrology Challenge
This article deals with the developments in the measurement and identification of conformality which is a key function in conformal doping. For this purpose this paper extensively uses SSRM to characterize the vertical/lateral junction depths, concentration levels and degree of conformality. As a complement to the SSRM technique this paper developes a concept based on resistance measurements of fin's which allows to map the sidewall doping across the wafers and provides fast feedback on conformality. The concept uses the reduction of the sheet resistance of a fin which was covered with a hardmask during the implantation, as a measure for the degree of side wall doing. The concept is supported by theoretical simulations and verified using tilted implants.
W.Vandervorst, P.Eyben, M.Jurzack, B.Pawlak, R.Duffy
[International Symposium on VLSI Technology, Systems and Applications, 2008, p. 158]

May. 18, 2008Material Aspects and Challenges for SOI FinFET Integration
M. J. H. van Dal, G. Vellianitis, R. Duffy, B. J. Pawlak, L-S Lai, A. Hikavyy, N. Collaert, M. Jurczak, R. J. P. Lander
[213th ECS Meeting, Abstract 636, © The Electrochemical Society]

May. 14, 2008From Gate-All-Around to nanowire MOSFETs
The classical MOSFET is reaching its scaling limits and "end-of-roadmap" alternative devices are being investigated. Amongst the different types of SOI devices proposed, one clearly stands out: the multigate field-effect transistor (multigate FET). This device has a general "wire-like" shape. Multigate FETs are commonly referred to as "multi(ple)-gate transistors", "FinFETs", "tri(ple)- gate transistors", "GAA transistors", etc. This paper describes the reasons for evolving from single-gate to multi-gate structures. It also describe some issues in ultra-small devices, such as doping fluctuation effects and quantum confinement effect.
J.P. Colinge
[International Semiconductor Conference, Sinaia, Romania, pp. 11-17, Oct. 2007]

May. 13, 2008ESD Sensitivity of 65-nm Fully Depleted SOI MOSFETs with Different Strain-Inducing Techniques
The role of this study is to further investigate the ESD sensitivity of new a generation 65-nm Fully Depleted SOI MOSFETs, with particular attention to the strain engineering. The focus is on the devices that need to be protected from ESD, rather than on the protection structures themselves. A detailed electrical investigation is carried out in order to classify the observed failure modes and mechanisms. We propose a new failure criterion based on sub-threshold drain current that allows us to univocally identify the device failure (i.e. filament between source and drain and/or gate-oxide breakdown). Finally, we show that the failure voltage depends on the strain level and the gate length, indicating that the strain-engineering may have a non-marginal impact on the reliability of advanced CMOS devices. Furthermore, we show the absence of filament in sCESL+SOI MOSFETs.
A. Griffoni, A. Tazzoli, S. Gerardin, G. Meneghesso, E. Simoen and C. Claeys
[International ESD Workshop, 2008]

May. 7, 2008FinFET technology for analog and RF circuits
FinFET technology presents a competitive alternative to planar CMOS as it features a better control of the short channel effects. This results in improved digital and analog performances. The radio-frequency (RF) behavior is however affected by a large level of parasitics. In this paper, we explain how technological options and device design affect the FinFET performance. In addition, the challenges and opportunities for both wideband modeling and the design of analog and RF circuits are identified and discussed.
B. Parvais, V. Subramanian, A. Mercha, M. Dehan, P. Wambacq, W. Sanssen, G. Groeseneken, S. Decoutere
[14th IEEE International Conference on Electronics, Circuits and Systems, 2007, pp.182-185]

Apr. 29, 2008Quantum-mechanical effects in nanometer scale MuGFETs
Solving the Poisson and Schrödinger equations self-consistently in two dimensions reveals quantum-mechanical effects that influence the electron concentration, the threshold voltage and the subthreshold slope of MuGFETs. The average electron concentration needed to reach the threshold voltage depends on the gate configuration and on the device geometry. The dependence of the energy of the subbands on the different gate configurations is studied, and the relation between threshold voltage and the lowest subband energy is investigated. Due to a dynamic threshold voltage effect, the drain current is lower in the quantum-based drain current model than in classical simulations. This dynamic increase of threshold voltage is due to an increase of the subband energy with the electron concentration. This effect degrades the subthreshold slope. It is observed in non-symmetrical devices (FinFET, tri-gate), but not in symmetrical structures (GAA). This gives symmetrical devices like GAA nanowires an intrinsic advantage compared to the other types of devices.
Se Re Na Yun, Chong Gun Yu, Jong Tae Park, Jean Pierre Colinge
[Microelectronic Engineering Vol. 85, pp. 1717–1722, 2008]

Apr. 3, 2008Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors
The minimum energy of the first conduction subband varies with gate voltage in trigate silicon-on-insulator metal-oxide-silicon field-effect transistors (MOSFETs) in subthreshold operation. In an inversion-mode trigate device, the energy level of the lowest subband increases with electron concentration, while it decreases under the same conditions in some accumulation-mode devices. As a result of this quantum effect, the subthreshold swing of accumulation-mode trigate FETs is smaller than predicted by classical theory. This effect is not observed in fin-shaped FETs and gate-all-around MOSFETs and can be amplified by modifying the device cross section. Jean-Pierre Colinge, Aryan Afzalian, Chi-Woo Lee, Ran Yan, and Nima Dehdashti Akhavan
[Applied Physics Letters 92, 133511, 2008]

Mar. 15, 2008The New Generation of SOI MOSFETs
[Romanian Journal of Information Science and Technology, Volume 11, Number 1, 2008, pp. 3-15]

Feb. 3, 2008Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies
CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.
Wambacq, P.; Mercha, A.; Scheir, K.; Verbruggen, B.; Borremans, J.; De Heyn, V.; Thijs, S.; Linten, D.; Van der Plas, G.; Parvais, B.; Dehan, M.; Decoutere, S.; Soens, C.; Collaert, N.; Jurczak, M.
[ISSCC 2008. Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 2008]

Jan. 23, 2008Doping Fluctuation Effects in Trigate SOI MOSFETs
Random doping fluctuation effects are studied in n-channel Trigate SOI MOSFETs using numerical simulations. The presence of a single positive doping impurity atom increases the threshold voltage. Electrical parameters vary with the polarity and the physical location of the impurity atom.
Ran Yan, Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee, and Jean-Pierre Colinge
[Proceeding 4th EuroSOI Workshop, pp.65-66 , 2008]

Jan. 23, 2008Evidence for Substrate Bias Effects in SOI ΩFETs
It is generally accepted that, due to strong coupling of the lateral gates, narrow SOI Multiple-Gate FETs (MuGFETs) are immune to substrate effects [1]-[3]. Nevertheless, in this work we present experimental evidence for significant substrate bias effects in narrow SOI ΩFETs, consisting in the strong variation of the drive current, transconductance and gate-induced drain leakage current (GIDL), with invariant threshold voltage, subthreshold slope and DIBL. The origin and possible implications of the observed effects are discussed.
T. Rudenko, V. Kilchytska, N. Collaert, M. Jurczak, A. Nazarov and D. Flandre
[EUROSOI Workshop Proceedings: 4th Workshop of the Thematic Network on Silicon-on-Insulator Technology, Devices and Circuits, 2008, pp. 137-138]

Jan. 23, 2008Hydrogen as Source of High-Temperature Charge Instability in the Buried Oxide of SOI Structures and MOSFETs
A. Nazarov, V. Lysenko, D. Flandre and J.P. Colinge
[Proceeding 4th EuroSOI Workshop, pp.113-114 , 2008]

Jan. 23, 2008Influence of Carrier Confinement on the Subthreshold Swing of Multigate SOI MOSFETs
The minimum energy of the first conduction subband varies with gate voltage in trigate SOI MOSFETs in subthreshold operation. In an inversion-mode device, the energy level of the lowest subband increases when the electron concentration increases, while it decreases under the same conditions in some accumulation-mode devices. As a result of this quantum effect, the subthreshold swing of accumulation-mode trigate FETs is smaller than predicted by classical theory, while that of inversion-mode devices is higher. This effect is not observed in FinFETs and GAA MOSFETs and can be amplified by modifying the device cross section.
Jean-Pierre Colinge, Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee and Ran Yan
[Proceeding 4th EuroSOI Workshop, pp.61-62 , 2008]

Jan. 23, 2008Ultra Scaled MultiGate SOI MOSFETs: Accumulation-Mode vs. Inversion-Mode
The performances of accumulation-mode and inversion-mode Multigate FETs in ultra scaled devices are compared through device simulations. We show that for sub 10nm cross dimensions, device performances (subthreshold slope, threshold voltage…) depend mainly on cross section size and bias voltage and very little on channel doping.
Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee, Ran Yan and Jean-Pierre Colinge
[Proceeding 4th EuroSOI Workshop, pp.47-48, 2008]

Jan. 23, 2008Unusual noise behavior versus temperature in nFinFETs on silicon on insulator (SOI) substrates processed with different strain techniques
The impact of strain techniques on the low frequency (LF) noise in nFinFETs on SOI substrates devices is reported. Five process conditions with different stressor methods are studied. A carrier number fluctuation dominant flicker noise has been observed for all devices studied. An unusual noise spectrum was observed specifically for the devices which received a Selective Epitaxial Growth (SEG) process. A detailed study of noise versus temperature (150K-300K) was performed on these devices.
Guo, W.; Routoure, J.; Cretu, B.; Carin, R.; Simoen, E.; Mercha, A.; Collaert, N.; Put, S. and Claeys, C.
[EUROSOI Workshop Proceedings: 4th Workshop of the Thematic Network on Silicon-on-Insulator Technology, Devices and Circuits, 2008, pp. 141-142]

Jan. 1, 20083D simulation of Nanowire by Full-Real Space NEGF Simulator
In this article, we present the effects of device parameters variations on the electrical characteristics of rectangular Nanowire. Our three dimensional (3D) device simulator is based on the Non Equilibrium Green Function (NEGF) formalism. Starting from a basic structure GAA Nanowire with a gate length of 10 nm, variation of gate length and channel thickness was carried out in connection with the numerical calculation of device characteristics. In this work Quantum transport equations are solved in 3D by NEGF method in active area of the device to obtain the charge density and Poisson’s equation is solved in entire domain of simulation to get potential profile.
Nima Dehdashti, Aryan Afzalian, Chi-Woo Lee, Ran Yan, G. Fagas and Jean-Pierre Colinge
[Tyndall National Institute]

Jan. 1, 2008Comparison of different surface orientation in narrow fin MuGFETs
Chi-Woo Lee, A. Afzalian, Ran Yan, Nima Dehdashti, J.P. Colinge, Weize Xiong
[Abstracts of the 14th International Symposium on the Physics of Semiconductors and Applications (ISPSA), Jeju, Korea, p. 282 (2008)]

Jan. 1, 2008FinFETs and Other Multi-Gate Transistors
Series: Series on Integrated Circuits and Systems
Jean-Pierre Colinge (Ed.)

2008, XVI, 340 p., Hardcover
ISBN: 978-0-387-71751-7
Summary (as given on the Springer website): "FinFETs and Other Multi-Gate Transistors" provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits.

Dec. 17, 2007Equivalent Circuit Based Non-linear Microwave Model for FinFETs
Equivalent circuit based non-linear microwave modelling is studied for the case of FinFET devices. Firstly, an accurate multi-bias small signal equivalent circuit is extracted and then used for building a non-linear full blown lookup table model. Subsequently, an alternative model implementation, which is based on empirical functions, has been investigated. A fully validation of the extracted non-linear models is achieved by comparing their simulation results with large signal measurements.
G. Crupi, D. M. M.-P. Schreurs, I. Angelov, A. Caddemi and B. Parvais
[ISMOT 2007]

Dec. 12, 2007Effects of Heavy-Ion Strikes on Fully Depleted SOI MOSFETs With Ultra-Thin Gate Oxide and Different Strain-Inducing Techniques
We study the immediate and long-term effects of heavy-ion strikes on 65-nm Fully Depleted SOI MOSFETs with different strain engineering solutions. Some of the phenomena already present in bulk devices, such as drain current collapse, are still observed alongside some new long-term effects concerning the degradation kinetics under electrical stress. On the other side, early breakdown seems to vanish. SOI degradation after heavy-ion strikes and during following electrical stress is shown to depend on the strain level and strain-inducing technique. We interpreted these results in terms of radiation-induced defects in the gate and isolation oxide.
Griffoni, A.; Gerardin, S.; Cester, A.; Paccagnella, A.; Simoen, E.; Claeys, C.
[IEEE Transactions on Nuclear Science, Vol. 54, Issue 6, pp. 2257-2263]

Dec. 12, 2007Geometry and Strain Dependence of the Proton Radiation Behavior of MuGFET Devices
The proton irradiation effects on n-MuGFET devices with three different geometries (single fin, wide fin and multiple fin) are studied. Also, the effect of tensile strain in the fin on the radiation behavior is investigated. A fundamental difference in the radiation behavior between the non-strained and the strained devices is found. The degradation of the strained devices is most affected by the mobility decrease of the backside transistor. The non-strained devices show a much lesser back gate mobility degradation. For these devices the creation of positive oxide traps is dominant. This shifts the onset of the back channel to lower gate voltages, inducing a transconductance increase at intermediate gate voltages. This effect is less pronounced for single fin MuGFETs. At higher gate voltage, the transconductance decreases for the strained and increases for the non-strained transistors.
Put, S. Simoen, E. Collaert, N. Claeys, C. Van Uffelen, M. Leroux, P.
[IEEE Transactions on Nuclear Science. Vol. 54, Issue 6, pp. 2227-2232]

Dec. 12, 2007Understanding the optimization of sub-45nm FinFET devices for ESD applications
ESD performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing. Thermal issues are experimentally correlated to gate length, fin width, electrical operation mode and are investigated by TCAD simulation. S/D implant conditions, silicide blocking, and selective epitaxial growth are studied. Reasonable ESD performance is demonstrated while margins between success and failure seem to be very narrow.
D. Trémouilles, S. Thijs, C. Russ, J. Schneider, C. Duvvury, N. Collaert, D. Linten, M. Scholz, M. Jurczak, H. Gossner, G. Groeseneken
[29th Electrical Overstress/Electrostatic Discharge Symposium, 2007, pp. 7A.5-1-7A.5-8]

Dec. 1, 2007Geometry and Strain Dependence of the Proton Radiation Behavior of MuGFET Devices
The proton irradiation effects on n-MuGFET devices with three different geometries (single fin, wide fin and multiple fin) are studied. Also, the effect of tensile strain in the fin on the radiation behavior is investigated. A fundamental difference in the radiation behavior between the non-strained and the strained devices is found. The degradation of the strained devices is most affected by the mobility decrease of the backside transistor. The non-strained devices show a much lesser back gate mobility degradation. For these devices the creation of positive oxide traps is dominant. This shifts the onset of the back channel to lower gate voltages, inducing a transconductance increase at intermediate gate voltages. This effect is less pronounced for single fin MuGFETs. At higher gate voltage, the transconductance decreases for the strained and increases for the non-strained transistors.
Put, S. Simoen, E. Collaert, N. Claeys, C. Van Uffelen, M. Leroux, P.
[IEEE Transactions on Nuclear Science. Volume: 54, Issue: 6 pp. 2227 - 2232]

Nov. 5, 2007Analytical Extraction of Small and Large Signal Models for FinFET Varactors
In this work we report on the small and large signal behaviour of advanced nMOS varactors fabricated in FinFET technology. This is the first paper showing large signal network analyzer (LSNA) measurements performed on FinFET varactors. These nonlinear measurements are modeled with a lookup table based model that is constructed using an accurate multi-bias small signal equivalent circuit. The validity of the extracted small and large signal models is verified through the very good agreement between measurements and simulations.
Giovanni Crupi, Dominique M. M.-P. Schreurs, Morin Dehan, Dongping Xiao, Alina Caddemi, Abdelkarim Mercha and Stefaan Decoutere
[Solid-State Electronics, Vol. 52, Issue 5, pp. 704-710 ]

Nov. 5, 2007ESD protection for sub-45 nm MugFET technology
From the design point of view, while such technology options may result in increased transistor performance, the ability to achieve sufficient product reliability is to be addressed. Among the industry accepted reliability requirements, electrostatic discharge (ESD) reliability assessment is the focus of this work.
M.I. Natarajan, S. Thijs, D. Tremouilles, D. Linten, N. Collaert, M. Jurczak, G. Groeseneken
[14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007, pp. 159-164]

Oct. 22, 2007A Quantum Definition of Threshold Voltage in MuGFETs
The dependence of threshold voltage on device dimensions and number of gates is analyzed. A new definition of threshold voltage, based on quantum-mechanical considerations, is proposed.
Se Re Na Yun, Chong Gun Yu, Jong-Tae Park, Chi-Woo Lee, D. Lederer, A. Afzalian, Ran Yan, J.P. Colinge
[Proceedings IEEE International SOI Conference, pp. 137-138, (2007)]

Oct. 22, 2007Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET
The origin of the large Vt shift observed in planar FDSOI is the creation of negative charge states in the BOX by F implant. F implant is a suitable approach for planar FDSOI SoC integration with single WF metal gate, but NOT for MuGFETs. F implant degrades electron mobility and the degradation is a function of F dose. The hole mobility is unaffected by F implant.
W. Xiong, C.H. Hsu, C.R. Cleavelin, M. Ma, P. Patruno, C-W. Lee, R. Yan, D. Lederer, A. Afzalian, J.P. Colinge
[Proceedings IEEE International SOI Conference 2007, pp. 35-36, (2007)]

Oct. 22, 2007Multi-Gate SOI MOSFET Operations in Harsh Environments
This paper reviews MuGFET (multi-gate MOSFET) devices performance under extreme temperature range (5-573 K) and total radiation dose up to 6 Mrad. It is concluded that MuGFET is not only a good platform for CMOS scaling, but also an excellent platform for operation in harsh environments.
W. Xiong, C. R. Cleavelin, C.H. Hsu, M. Ma, T.Schulz, K. Schruefer, P. Patruno, J.P. Colinge
[Proceedings IEEE International SOI Conference, pp. 29-30, (2007)]

Oct. 22, 2007Study of Fin Profiles and MuGFETs built on SOI Wafers with a Nitride-Oxide Buried Layer (NOx-BL) as the Buried Insulator Layer
Multiple-gate-MOSFETs (MuGFET) have better short-channel effects (SCE) control than planar MOSFET and MuGFETs are good candidates to replace planar bulk MOSFET for low power applications. A key feature in the MuGFETs is the recess and undercut of the fins in the buried oxide. Undercut improves gate control of the channel at fin and BOx interface, but also undermines the fin stability, and increases susceptibility to gate etch defects. This paper introduces SOI wafers with nitride buried dielectric that eliminates the undercut, while maintaining good gate control of the channel through higher buried insulator dielectric constant.
P. Patruno, M. Kostrzewa, K. Landry, W. Xiong, C. R. Cleavelin, C. H. Hsu, M. Ma, J. P. Colinge
[Proceedings IEEE International SOI Conference, pp. 51-52, (2007)]

Oct. 1, 20073D Simulation of Doping Fluctuation Effects in Trigate FETs
Ran Yan, Danny Lynch, Thibault Cayron, Dimitri Lederer, Aryan Afzalian, Chi-Woo Lee, J.P. Colinge
[Comsol Conference, Grenoble, France, Oct. 2007]

Oct. 1, 2007Dose rate dependence of the back gate degradation in thin gate oxide PD-SOI MOSFETs by 2-MeV electron irradiation
The degradation of the electrical properties of thin gate oxide PD-SOI n-MOSFETs by 2-MeV electrons at different dose rates is presented. The degradation of the back channel and its dependence on dose rate are clarified. The characteristics of the PD-SOI MOSFETs are degraded, and the degradation becomes higher for a low dose rate. The magnitude of the hysteresis characteristics in the drain current becomes smaller after irradiation, and the degradation for a low dose rate is higher than for a high dose rate. It is found that the degradation of the front characteristics is related to the back gate degradation by the coupling effect.
K. Hayama, K. Takakura, M. Yoneoka, H. Ohyama, J.M. Rafí, A. Mercha, E. Simoen and C. Claeys
[Microelectronic Engineering, Vol. 84, Issues 9-10, pp. 2125-2128]

Sep. 1, 2007Specific features of multiple-gate MOSFET threshold voltage and subthreshold slope behavior at high temperatures
In this paper specific features of the multiple-gate MOSFETs (MuGFETs) behavior at high temperatures (up to 300 °C) are analyzed through measurements, 2D simulations and analytical models of long-channel transistors. The high-temperature evolutions of threshold voltage and subthreshold slope are discussed paying particular attention to the influence of Si film thinning. High-temperature behavior of the threshold voltage and subthreshold slope in MuGFETs is demonstrated, for the first time, to be different from those generally considered for FD SOI MOSFETs. It is shown that the threshold voltage shift with temperature is strongly attenuated in MuGFETs and further decreases with Si film thinning. Then, the deviation of the MuGFET subthreshold slope at high temperatures from the expected ideal linear temperature dependence is analyzed and the possible reasons are discussed.
V. Kilchytska, N. Collaert, M. Jurczak, D. Flandre
[Solid-State Electronics, EUROSOI ’07 Conference, Vol. 51, Issue 9, pp. 1185-1193]

Sep. 1, 2007Substrate Bias Effect Linked to Parasitic Series Resistance in Multiple-Gate SOI MOSFETs
It is generally recognized that very narrow silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) are insensitive to substrate bias due to the strong electrostatic gate control. In this letter, we demonstrate, for the first time, that, in short-channel narrow FinFETs, substrate bias can dramatically change the on-current without change in the threshold voltage, subthreshold slope, and drain-induced barrier lowering, due to the modulation of the parasitic series resistance. Therefrom, contrary to general belief, very narrow short-channel multiple-gate field-effect transistors can be sensitive to substrate-related effects (buried oxide formation, irradiation, etc). Another important implication of the described effect is related to the diagnostics of the series resistance in SOI FinFETs and better prediction of their full intrinsic performance potential.
Tamara Rudenko, Valeria Kilchytska, Nadine Collaert, Malgorzata Jurczak, Alexey Nazarov, and Denis Flandre
[IEEE Electron Device Letters, Vol. 28, Issue 9, pp. 834-836]

Aug. 28, 2007Gate induced floating body effects in TiN/SiON and TiN/HfO2 gate stack triple gate SOI nFinFETs
In this paper, the appearance of gate induced floating body effects in triple gate SOI nFinFETs with TiN/SiON and TiN/HfO2 gate stacks is investigated. Different floating body effects (FBEs) are found to appear under moderate accumulation back gate bias (VBG) conditions in devices with wide and long enough geometries. In particular, a second peak in the linear transconductance (gmf), associated with electron valence band (EVB) direct tunneling, is observed in TiN/SiON devices for front gate voltages (VFG) around 0.8 V. Interestingly, in spite of showing about two orders of magnitude lower total gate current, a second peak in gmf is also found in TiN/HfO2 devices for VFG around 1.1 V.
Under the accumulation VBG conditions in which FBEs are observed, front gate switch drain current (ID) transients are also appreciated. Interestingly, a change in the shape of ID transients is observed for VFG conditions in which EVB majority carriers are injected into the floating fin. The ID transients, as well as the second peak of gmf and other FBEs, are found to gradually diminish for strong accumulation VBG conditions or reduced geometry dimensions.
J.M. Rafí, E. Simoen, A. Mercha, N. Collaert, K. Hayama, F. Campabadal, C. Claeys
[Solid-State Electronics Vol. 51, Issue 9, pp. 1201-1210]

Jul. 2, 2007Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL
In this paper, we investigate for the first time the impact of raised source/drain on the short channel current enhancement of MuGFET devices on super critical strained SSOI (SC-SSOI). Short channel nMOS drive current can be improved up to 15% and even 50% in the case of high tensile 30 nm SSOI substrates. We also show that SC-SSOI has a higher sensitivity to the mobility boost from tensile contact etch stop layers (CESL). Therefore the combination of both mobility boosters is very beneficial for nMOS MuGFET when used with SEG.
Collaert, N. Rooyackers, R. Dilliway, G. Iyengar, V. Augendre, E. Leys, F. Cayrefourq, I. Ghyselen, B. Loo, R. Jurczak, M. Biesemans, S. IMEC, Leuven
[International Symposium on VLSI Technology, Systems and Applications, 2007, pp. 1-2]

Jul. 1, 2007Simulation of fluorine implant effects in metal-gate FD-SOI and MuGFETs
Fluorine (F) implantation creates negative charges at the Si/SiO₂ interface in FDSOI transistors[1]. This paper describes simulation of the influence of F Implant on Threshold Voltage (Vth) for Metal Gate FDSOI and MuGFETs using FEMLABⓇ. The origin of the large Vth shift observed in planar FDSOI due to is the creation of negative charge states in the BOX by the F implant. F implant is a suitable approach for planar FDSOI SoC integration with single work function (WF) metal gate, but NOT for MuGFETs.
Chi-Woo Lee, D. Lederer, A. Afzalian, Ran Yan, J.P. Colinge
[Proceedings IEEK 2007 Summer Conference, Korea (2007)]

Jul. 1, 2007Stress Hybridization for Multigate Devices Fabricated on Supercritical Strained-SOI (SC-SSOI)
In this letter, we investigate the impact of a hybridized strain technology on the performance of FinFET-based multigate field-effect transistors (MUGFETs). The technology combines the use of supercritical strained-silicon-on-insulator (SC-SSOI) and strained contact etch stop layers (CESLs). We will show that SC-SSOI (top plane orientation ) with tensile CESL (tCESL), when used for MUGFET, leads to higher improvement in electron mobility as compared to standard SOI with tCESL. Therefore, the combination of both mobility boosters is very beneficial for n-channel MOS MUGFET. However, the impact of compressive CESL on p-channel MOS (pMOS) performance is strongly reduced and becomes even negative when used on an SC-SSOI substrate. Local strain relief of the SC-SSOI substrate is mandatory in order to achieve good pMOS device performance.
Collaert, N. Rooyackers, R. De Keersgieter, A. Leys, F.E. Cayrefourcq, I. Ghyselen, B. Loo, R. Jurczak, M.
[IEEE Electron Device Letters, Vol. 28, Issue 7, pp. 646-648 ]

Jun. 13, 2007Solid phase epitaxy versus random nucleation and growth in sub-20 nm wide fin field-effect transistors
The authors investigate the implications of amorphizing ion implants on the crystalline integrity of sub-20 nm wide fin field-effect transistors (FinFETs). Recrystallization of thin body silicon is not as straightforward as that of bulk silicon because the regrowth direction may be parallel to the silicon surface rather than terminating at it. In sub-20 nm wide FinFETs surface proximity suppresses crystal regrowth and promotes the formation of twin boundary defects in the implanted regions. In the case of a 50 nm amorphization depth, random nucleation and growth leads to polycrystalline silicon formation in the top ~25 nm of the fin, despite being only ~25 nm from the crystalline silicon seed.
R. Duffy, M. J. H. Van Dal, B. J. Pawlak, M. Kaiser, R. G. R. Weemaes, B. Degroote, E. Kunnen and E. Altamirano
[Applied Physics Letters, Vol. 90, Issue 24]

Jun. 12, 2007Renesas Technology Develops Promising Technology for Implementing On-Chip SOI SRAM of 32-Nanometer Generation and Beyond
[Design & Reuse]

Jun. 5, 2007Carrier lifetime analysis in thin gate oxide FD-SOI n-MOSFETs by gate-induced drain current transients
The drain current (ID) transients by switching the biasing condition are examined in FD-SOI MOSFETs with negative biased back gate voltage (VBG). Special attention is paid to the influence of the gate-induced charge/discharge of the floating body on the ID transient. The ID transient appears not only by switching the front gate voltage (VFG) but also by switching VBG. It is also shown that the analysis of a small VFG step transient is useful to examine the lifetime under different bias conditions. All the results can be explained by the transitional change of ID − VFG characteristics at different body-charge conditions.
K. Hayama, K. Takakura, H. Ohyama, J. M. Rafí, A. Mercha, E. Simoen, C. Claeys
[Journal of Materials Science: Materials in Electronics, Vol. 19, Issue 2, pp. 161-165]

May. 30, 2007Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs
The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.
J. M. Rafí, E. Simoen, A. Mercha, K. Hayama, F. Campabadal, H. Ohyama, C. Claeys
[Microelectronic Engineering Vol. 84, Issues 9-10, pp. 2081-2084]

May. 30, 2007Multi-gate SOI MOSFETs
This paper describes the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, Π-gate, Ω-gate and gate-all-around) structures. Increasing the “effective number of gates” improves the electrostatic control of the channel by the gate and, hence, reduces short-channel effects. Due to the very small dimensions of the devices, one-and two-dimensional confinement effects are observed, which results in the need of developing quantum modeling tools for accurate prediction of the electrical characteristics of the devices.
J.P. Colinge
[Microelectronic Engineering, Vol. 84 (9-10), pp. 2071–2076, 2007 (Invited paper at INFOS 2007)]

May. 6, 2007Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications
MuGFET structure improves local transistor mismatch comparedto planar bulk MOSFET. This enables further SRAM cell sizereduction. GIDL current is well controlled even with a mid-gapmetal gate. MuGFETs have low subthreshold leakage if Lg/Wsiratio is kept above 1.5. The advantage of MuGFET subthresholdleakage suppression is even more pronounced at highertemperatures. Furthermore MuGFETs are compatible with localstrain techniques to improve carrier mobility. The aforementionedqualities, along with low manufacturing cost of single mid-bandgapmetal gate, make MuGFET a good candidate to replace planarbulk MOSFET for Low-Power Applications.
by Weize Xiong, C. Rinn Cleavelin, Che-Hua Hsu, Mike Ma, K. Schruefer, Klaus Von Armin, T. Schulz, I. Cayrefourcq, C. Mazure, P. Patruno, M. Kennard, Kyoungsub Shin, Xin Sun, Tsu-Jae King Liu, K. Cherkaoui and J.P. Colinge
[Electrochemical Society Transactions, Vol. 6 (4), pp. 59-69, 2007]

May. 6, 2007Temperature Influences on FinFETs with Undoped Body
This work presents a study, based on DC measurements, of the temperature influence on the performance of nMOS triple-gate FinFETs with high-K dielectrics, TiN gate material and an undoped body. FinFETs show smaller threshold voltage variations with temperature than planar fully-depleted SOI MOSFETs. The subthreshold slope reduced with the temperature and approached the ideal value at lower temperatures. In the temperature range under study the mobility increases linearly as the temperature is reduced and the dominating mobility degradation factor is phonon scattering. The DIBL has been evaluated and no temperature dependence has been found. Finally, the series resistance has been also extracted and demonstrates a reduction as the temperature is reduced due to the mobility improvement.
M. A. Pavanello, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert and C. Claeys
[ 211th ECS Meeting, Vol. 6, Issue 4, pp. 211-216]

Apr. 23, 2007Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk
Frequency variation of the output conductance in advanced fully depleted SOI and multiple-gate MOSFETs related to the electrical coupling between drain and Si substrate underneath the buried oxide (BOX) is analyzed through measurements and 2-D simulations. A low-frequency (LF) conductance variation in these devices, which could be erroneously attributed to the self-heating effect, is proved to be related to the presence of the Si substrate underneath the BOX. Suppression of this substrate-related LF transition in narrow-fin FinFET's output conductance is experimentally demonstrated. Furthermore, the substrate-related transitions are shown to be increasing with device downscaling, as well as BOX thinning, suggesting that this effect becomes more important for the future device generations.
Valeria Kilchytska, Guillaume Pailloncy, Dimitri Lederer, Jean-Pierre Raskin, Nadine Collaert, Malgorzata Jurczak, and Denis Flandre
[IEEE Electron Device Letters, Vol. 28, Issue 5, pp. 419-421]

Apr. 23, 2007Oki ultraviolet (UV) sensor IC ML 8511
In Chinese cell phone.
[OKI]

Apr. 17, 2007Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective
Based on careful physical description, the effect of gate-length downscaling on the RF performance of double-gate fin field-effect transistors (finFETs) has been analyzed. Downscaling is beneficial to the device RF performance although the losses due to series parasitics increase. The source/drain series resistance in finFET largely limits the device RF performance, and the losses due to the gate resistance increase with reducing gate length. Double-gate finFETs have the potential to reach the RF International Technology Roadmap for Semiconductor targets in the few decananometer regime, but meeting the specification for gate length in the order of 10 nm may require further improvements.
Sebastien Nuttinck, Bertrand Parvais, Gilberto Curatola, Abdelkarim Mercha
[IEEE Transactions on Electron Devices, Vol. 54, Issue 2, pp. 279-283]

Mar. 27, 2007Impact of fin width on digital and analog performances of n-FinFETs
This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs (I–V, C–V and 1/f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.
V. Subramanian, A. Mercha, B. Parvais, J. Loo, C. Gustin, M. Dehan, N. Collaert, M. Jurczak, G. Groeseneken, W. Sansen and S. Decoutere
[Solid-State Electronics Volume 51, Issue 4, April 2007, Pages 551-559]

Feb. 26, 2007Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation
This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
M.A. Pavanello, J.A. Martino, E. Simoen, R. Rooyackers, N. Collaert, C. Claeys
[Solid-State Electronics Vol. 51, Issue 2, pp. 285-291 ]

Feb. 12, 2007Subthreshold channels at the edges of nanoscale triple-gate silicon transistors
The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50×60×35 nm3. Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analyses, the authors conclude that subthreshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner effect.
H. Sellier, G. P. Lansbergen, J. Caro, S. Rogge, N. Collaert, I. Ferain, M. Jurczak and S. Biesemans
[Applied Physics Letters 90, 073502]

Jan. 1, 2007Low Temperature Operation of Undoped Body Triple-Gate FinFETs from an Analog Perspective
This paper studies the temperature reduction influence on some analogfigures of merit of n-type triple-gate FinFETs with undoped body, usingDC measurements. It is demonstrated that the temperature reductionimproves the transconductance over drain current ratio in any operationalregion. On the other hand, the output conductance is degraded when thetemperature is reduced. The combination of these effects shows that theintrinsic gain of a L=90 nm FinFET is degraded by 3 dB when thetemperature reduces from 300 K down to 100 K. A comparison withplanar single gate fully depleted SOI reveals that the temperaturedegradation of the output conductance in FinFETs is less temperature-dependent.
M. A. Pavanelloa, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert and C. Claeys
[The Electrochemical Society, 2007]

Jan. 1, 2007Quantum-Mechanical Effects in Nanometer Scale MuGFETs
Se Re Na Yun, Chong Gun Yu, Jong Tae Park, and J.P. Colinge
[Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), pp. 29-32, 2007]

Dec. 22, 2006Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density
We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H2 anneal) further reduce the CD to 13 nm.
B. Degroote, R. Rooyackers, T. Vandeweyer, N. Collaert, W. Boullart, E. Kunnen, D. Shamiryan, J. Wouters, J. Van Puymbroeck, A. Dixit, M. Jurczak
[Microelectronic Engineering Vol. 84, Issue 4, pp. 609-618]

Jan. 1, 2006Silicon-on-insulator lateral dual sidewall Schottky (SOI-LDSS) concept for improved rectifier performance: a two-dimensional simulation study
Purpose – To develop a silicon lateral Schottky rectifier with low forward voltage drop and low reverse leakage current while its breakdown voltage is significantly larger than that of a conventional Schottky rectifier.
Design/methodology/approach – A two-dimensional device simulation has been used, to examine the effect lateral dual sidewall Schottky concept on the current-voltage characteristics of a lateral Schottky rectifier on silicon-on-insulator. The Schottky contact consists of a low-barrier metal and a high-barrier metal.
Findings – Results show that, during forward bias, the low-barrier Schottky (LBS) contact conducts resulting in a low forward voltage drop. During the reverse bias, the LBS contact is shielded by the depletion region of the high-barrier Schottky contact resulting in a low reverse leakage current.
Practical implications – With this approach, silicon Schottky rectifiers with low power dissipation and improved breakdown voltage can be realized.
Originality/value – The proposed device has a large commercial potential as a low-power high-voltage switching device.
by M. Jagadesh Kumar, (Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India), C. Linga Reddy, (Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India)
[Emerald]

Mar. 1, 2005A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET – Two-dimensional Analytical Modeling and Simulation
[IEEE Trans. on Nanotechnology, Vol.4, pp. 260-268]

Aug. 26, 2004Processor benchmarks: Intel versus AMD = SOI power reduction
The power consumption of the Athlon 64 is lower than that of the Pentium 4 thanks to AMD's use of Silicon-on-Insulator (SOI) technology
[ZDNet.co.uk]