SOI fundamentals

Dec. 19, 2012Bulk vs SOI FinFET

Practical challenges of FinFETs: variability and manufacturability
[SOI Industry Consortium]

Jan. 25, 2011Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]

Nov. 29, 2010SOI Technology
This article explains the issues related to silicon-on-insulator technology. As the bulk silicon CMOS processes are reaching there limit in terms of device miniaturization and fabrication, SOI technology gives a good alternative to that. SOI technology is considered to take the CMOS processing to its ultimate scalability, and a brief review of work published by many research groups is presented in this paper. Firstly, technological development on fabrication of silicon–on-insulator wafers is presented. After that focusing upon CMOS technology, different types of SOI MOSFETs and related physical concepts are evaluated. Finally double gate MOSFET’s properties, and its pros and cons over bulk CMOS technology are explained.
[ISU Electrical and Computer Engineering Archives]

Nov. 1, 2009Comparing SOI and bulk FinFETs: Performance, manufacturing variability, and cost
[Solid State Technology]

Aug. 13, 2009White paper on Silicon On Insulator (SOI) implementation
by Narayana Murty Kodeti
[Infotech Enterprises Ltd.]

Jun. 22, 2009Roadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic
[UC Louvain]

Mar. 17, 2009Methodologies for comparing bulk and SOI process technologies for SoC designs
[SOI Industry Consortium]

Mar. 5, 2009SOI reliability advantage: Soft errors

Sep. 1, 2008Multi-gate devices for the 32nm technology node and beyond
Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on, planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET-based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.
N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L.-S. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B.J. Pawlak, R. Rooyackers, T. Schulz, K.T. San, N.J. Son, M.J.H. Van Dal, P. Verheyen, K. von Arnim, L. Witters, K. De Meyer, S. Biesemans and M. Jurczak
[Solid-State Electronics, Vol. 52, Issue 9, pp. 1291-1296]

Nov. 1, 2007Scaling the Challenge of Memory at 45nm and Below
By Jeff Lewis, VP Marketing, Innovative Silicon Inc.
[Chip Design Magazine]

Sep. 1, 2007Substrate Bias Effect Linked to Parasitic Series Resistance in Multiple-Gate SOI MOSFETs
It is generally recognized that very narrow silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) are insensitive to substrate bias due to the strong electrostatic gate control. In this letter, we demonstrate, for the first time, that, in short-channel narrow FinFETs, substrate bias can dramatically change the on-current without change in the threshold voltage, subthreshold slope, and drain-induced barrier lowering, due to the modulation of the parasitic series resistance. Therefrom, contrary to general belief, very narrow short-channel multiple-gate field-effect transistors can be sensitive to substrate-related effects (buried oxide formation, irradiation, etc). Another important implication of the described effect is related to the diagnostics of the series resistance in SOI FinFETs and better prediction of their full intrinsic performance potential.
Tamara Rudenko, Valeria Kilchytska, Nadine Collaert, Malgorzata Jurczak, Alexey Nazarov, and Denis Flandre
[IEEE Electron Device Letters, Vol. 28, Issue 9, pp. 834-836]

May. 30, 2007Multi-gate SOI MOSFETs
This paper describes the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, Π-gate, Ω-gate and gate-all-around) structures. Increasing the “effective number of gates” improves the electrostatic control of the channel by the gate and, hence, reduces short-channel effects. Due to the very small dimensions of the devices, one-and two-dimensional confinement effects are observed, which results in the need of developing quantum modeling tools for accurate prediction of the electrical characteristics of the devices.
J.P. Colinge
[Microelectronic Engineering, Vol. 84 (9-10), pp. 2071–2076, 2007 (Invited paper at INFOS 2007)]

May. 6, 2007Temperature Influences on FinFETs with Undoped Body
This work presents a study, based on DC measurements, of the temperature influence on the performance of nMOS triple-gate FinFETs with high-K dielectrics, TiN gate material and an undoped body. FinFETs show smaller threshold voltage variations with temperature than planar fully-depleted SOI MOSFETs. The subthreshold slope reduced with the temperature and approached the ideal value at lower temperatures. In the temperature range under study the mobility increases linearly as the temperature is reduced and the dominating mobility degradation factor is phonon scattering. The DIBL has been evaluated and no temperature dependence has been found. Finally, the series resistance has been also extracted and demonstrates a reduction as the temperature is reduced due to the mobility improvement.
M. A. Pavanello, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert and C. Claeys
[ 211th ECS Meeting, Vol. 6, Issue 4, pp. 211-216]

Dec. 6, 2006Hitachi – why SOI for mu
[Advanced Substrate News]

Jun. 1, 2006Strained SOI (sSOI)

Jan. 25, 2005SOI Device Technology
by Makoto Yoshimi, PhD
Language: Japanese
Publisher: ED Research, Co. (Tokyo, Japan)
Summary: This book covers the history of SOI, the floating body effect and a variety of LSI applications. An SOI pioneer (he began his research over 20 years ago for Toshiba), Makoto Yoshimi is now Chief Scientist of Soitec Asia. "This book describes what SOI is all about", he says, "and provides an introduction for device engineers and graduate students."

Dr. Shigeto Maegawa of Renesas Technology Corp. (Japan) notes that the book, "...captures the enthusiasm of the engineers who worked so tenaciously to make SOI a reality."