Articles, publications, books and short courses

Jan. 25, 2016Forum: FD-SOI and RF-SOI - Tokyo 2016
On Thursday January 21st 2016 leading companies joined the SOI Industry Consortium in the Takeda Hall in the University of Tokyo to organize a forum covering planar FD-SOI as well as RF-SOI and More than Moore technologies.

Sep. 21, 2015Forum: Design for FD-SOI - Shanghai 2015
On September 15th, 2015 the SOI Industry Consortium, VeriSilicon, the Shanghai Institute of Microsystem and Information Technology (SIMIT) and Shanghai Industrial µTechnology Research Institute (SITRI) organized with many sponsors The Shanghai FD-SOI Forum 2015: “Design for FD-SOI”.

Apr. 13, 2015Forum: 2015 Beyond Computing Symposium - Shanghai, China
SITRI and the SOI Consortium have co-organized a ‘Beyond Computing' Innovative Technologies Symposium on March 17, 2015 in Shanghai. The Symposium covered the topics of MEMS, Semiconductor manufacturing, RF and Power which are the important parts of the fast growing “More than Moore” industry. This one day closed door symposium has offered attendees the opportunity to meet the industry leaders in China.

Mar. 10, 2015Forum: 2015 FD-SOI and RF-SOI - San Francisco, USA
On February 27th, 2015, leading companies joined the SOI Industry Consortium in San Francisco to organize a forum covering planar FD-SOI as well as RF-SOI technologies. A broad range of technology and design leaders from across the industry presented compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.

Jan. 30, 2015Forum: 2015 FD-SOI and RF-SOI - Tokyo, Japan
On January 23rd, 2015, leading companies joined the SOI Industry Consortium in Tokyo to organize a forum covering planar FD-SOI as well as RF-SOI technologies. A broad range of technology and design leaders from across the industry presented compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.

Sep. 26, 2014Forum: 2014 FD-SOI - Shanghai, China
FDSOI 28nm has moved into the manufacturing and volume production phase. It offers the IC industry the unique features of being able to fabricate at competitive cost, ultra low power, high speed ICs. It is a game changer technology platform that brings new powerful elements to the designers and a strong differentiation potential at IC and system level. The goal of this international forum is to gather IC industry decision makers, technology owners, opinion leaders, market analysts to exchange and assess the opportunities that FDSOI technology brings to the ever changing field of mobility internet, internet of things with their increasing demand for ultra low power operation at high performance.

Sep. 1, 2014Good FD-SOI Summer Reading & Viewing
Over the summer, there have been a number of excellent posts on various sites related to FD-SOI, showing that interest is running ever higher. But, if you’ve been fortunate enough to have had some vacation time, you might have missed some of them, so here’s a brief listing to help you catch up.
[Advanced Substrate News]

Jun. 4, 2014Synopsys, STMicroelectronics and Samsung Collaborate to Accelerate Adoption of 28-nm FD-SOI Technology for SoC Design
Synopsys Galaxy Design Platform Enables Designers to Take Full Advantage of High-Performance and Low Power of 28-nm FD-SOI

Aug. 30, 2013New FD-SOI Design Group on LinkedIn
[Advanced Substrate News]

May. 15, 2013Sheffield firm gets funding to develop low power SRAM for finfet processes
[Electronics Weekly]

Apr. 25, 2013Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
The SOI Industry Consortium, IBM and GLOBALFOUNDRIES organized a forum focused on fully depleted technologies for highly energy-efficient System-on-Chip applications.
[SOI Industry Consortium]

Mar. 19, 2013DATE: FDSOI costs to match bulk by year end, says ST
[Tech Design Forum]

Mar. 15, 2013Can “Less than Moore” FDSOI provides better ROI for Mobile IC?

Feb. 21, 2013ST runs cool 3GHz FD-SOI processors
[Electronics Weekly Magazine]

Feb. 20, 2013STMicroelectronics 28nm FD-SOI Technology Hits 3GHz Operating Speed
[ST Life.augmented]

Feb. 20, 2013London Calling: FDSOI clocks at 3GHz
[EE Times]

Feb. 5, 2013ARM rates FDSOI process as "good technology"
[EE Times]

Jan. 20, 2013ST plans for Dresden FDSOI production
[EE Times]

Dec. 15, 2012Altera eyes FDSOI process for FPGAs
[EE Times]

Dec. 12, 2012FDSOI roadmap renames next node as 14-nm
[EE Times]

Dec. 11, 201228-nm FDSOI is production ready, says ST
[EE Times]

Jul. 13, 2012SOI Parity with CMOS Good News for IP Designers

Jul. 12, 2012SOI Becomes Essential At 20nm
[Low-Power Engineering]

Jul. 11, 2012Ecosystem emerges around new moble chip tech
A consortium touting fully depleted silicon-on-insulator (FDSOI) technology for mobile computing applications presented a united front this week in promoting the process technology as a viable alternative to Intel’s FinFET manufacturing approach.
[EE Times]

May. 21, 20120.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process
[Journal of Low Power Electronics and Applications]

Apr. 16, 2012Soitec provides affordable paths to higher performance, lower-power processors for mobile and consumer devices

Apr. 16, 2012Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors

Apr. 6, 2012ST-Ericsson announces next-gen NovaThor at 28nm, on FD-SOI

Mar. 13, 2012ST-Ericsson’s Next-gen NovaThor: This Year, at 28nm, on FD-SOI Wafers from Soitec
[Advanced Substrate News]

Dec. 6, 2011ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]

Nov. 7, 2011Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
[EDA360 Insider]

Mar. 30, 2011Performance Evaluation of FD-SOI Mosfets for Different Metal Gate Work Function
[International Journal of VLSI Design & Communication Systems (VLSICS), Vol. 2, No. 1 ]

Mar. 13, 2011Reliability Evaluation of Fully Depleted SOI (FDSOI) Technology for Space Applications
[A. K. Sharma (NASA/GSFC) and A. Teverovsky (QSS Group, Inc.)]

Feb. 24, 2011Planar FD-SOI CMOS: The Competitive Advantage Mobile Silicon Technology
Only Planar Fully-Depleted SOI CMOS Technology will enable the optimal Power-Performance-Area-Cost and Time-to-Market balance you need for your next generation Mobile Product development.
[SOI Industry Consortium]

Feb. 15, 2011FD-SOI Technology Promises Power Advantages for Next-Generation Apps
[Mobile Dev & Design]

Feb. 15, 2011Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips
[Horacio Mendez, Executive Director, SOI Industry Consortium]

Feb. 3, 2011MEMC SOI Capability and Fully Depleted SOI Readiness

Dec. 30, 2010Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate
Components Research, Logic Technology Development, Intel Corporation

Dec. 27, 2010Planar fully depleted SOI: the technological solution against variability
It is well known that the planar fully depleted silicon-on-insulator (SOI) (FDSOI) architecture is a technological booster of the CMOS performance, thanks to better electrostatics than devices on bulk. This article shows that it also greatly improves the variability of the electrical characteristics, thanks to an undoped channel. This leads to good matching performance.
[Solid State Technology]

Dec. 14, 2010Will Future Transistors Appear in Glorious 3D?
[The Applied Materials Blog]

Nov. 1, 2010Short course: Subthreshold-Operation FDSOI. Transistors for Ultralow-Power Electronics
[S. A. Vitale, 2010 IEEE International SOI Conference]

Oct. 10, 2010Fully Depleted SOI for evolutionary planar device scaling
by Carlos Mazure and Christophe Maleville, Soitec

Jul. 21, 2010FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics
Silicon-on-insulator devices designed for optimum operation at 0.3 V promise longer operational life than conventional application-specific integrated circuits.
[By Steven A. Vitale, Peter W. Wyatt, Member IEEE, Nisha Checka, Jakub Kedzierski, and Craig L. Keast]

Jan. 1, 2006Book: Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications
31 of Japan's leading FD-SOI experts explain design for ultra-low-power applications. Leading experts expect the next-generation of device technology for ultra-low-power applications to be based on FD (fully-depleted) SOI MOSFETs. For circuit designers and university students who would like to learn about FD-SOI design, and get a basic understanding of the material technology and device physics, 31 experts from Japan have written a new textbook. It provides examples of unique circuit designs for ultra-low-power applications, as well as a brief history of SOI material technology and the basic operational mechanism of FD-SOI MOSFETs.
[by Sakurai, Takayasu, Matsuzawa, Akira, Douseki, Takakuni, 2006, XV, 411 p., Hardcover, ISBN: 978-0-387-29217-5]