FD-SOI Workshop 2013 - Kyoto, Japan

Leading member companies from the SOI Industry Consortium conducted a workshop covering planar FD-SOI technologies – ideally suited for highly energy-efficient system-on-chip (SOC) devices – on June 15, 2013 in Kyoto, Japan. The event ran just after the Japan Society for the Promotion of Science (JSPS) Symposium on low-voltage devices and circuits, which was being held during the same week as the VLSI Symposia.

Several technology and design leaders presented compelling solutions using FD-SOI technology, which is available today for the 28nm node, including competitive comparisons and product results.

This workshop was co-organized by Horacio Mendez from the SOI Consortium, Philippe Magarshack and Joel Hartmann from STMicroelectronics, and Mike Noonen from GLOBALFOUNDRIES.


> SoC Differentiation using FD-SOI – A Manufacturing Partner’s Perspective, by Shigeru Shimauchi, Country Manager, GlobalFoundries Japan

> Ultra Thin Body and Buried oxide substrate supply chain, by Nobuhiko Noto (SEH)

> Architectural choices & design-implementation methodologies for exploiting extended FD-SOI DVFS & body-bias capabilities, by David Jacquet (STMicroelectronics)

> Elements for the Next Generation FinFET CMOS Technology, by Terence Hook (IBM)

> 28nm FD-SOI Industrial Solution: Overview of Silicon Proven Key Benefits, by Laurent Le Pailleur (STMicroelectronics)