SOI Applications
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Updated: April 30, 2012
SOI Fundamentals
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
Design/IP
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
Analog/HV/RF
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Photonics
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
Power
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
Sensors/MEMS
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News ]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
Consortium Website – What’s New
#19 – Spring/Summer 2012
Special Edition: FD-SOI Industrialization
- Technology: ST/Soitec white paper excerpts
- Apps – ST-Ericsson's NovaThor at 28nm (interview)
- 20nm & Beyond: Chenming Hu; Leti
- Wafers: Soitec's Roadmap
- SOI Consortium – benchmarking
Press releases
Mentor Graphics to join the SOI Industry Consortium
Expands EDA Industry Support for Energy-Efficient SOI Technology
Download this press release
in pdf format
Boston, MA, November 12, 2009 – The SOI Industry Consortium, aimed at accelerating silicon-on-insulator (SOI) innovation into broad markets, announced today that Mentor Graphics Corporation (Nasdaq: MENT) has joined the worldwide organization. Mentor is a global leader in electronic hardware and software design solutions. As an active member and a leader in design enablement, Mentor will expand EDA tool and methodology support for SOI technology. This engagement connects Mentor’s strengths in low-power solutions with the inherent energy-efficiency benefits of SOI technology.
“Mentor Graphics is pleased to join the SOI Industry Consortium, and looks forward to advancing design automation support for SOI-based products and systems in collaboration with other members," said Robert Hum, VP and GM, Deep Submicron Technologies at Mentor Graphics. “As we engage our expertise in modeling, characterization, analytics and constructive design tools with the needs of the global SOI user community, we can help designers and manufacturers exploit all of the underlying goodness of SOI technology.”
“We welcome Mentor Graphics as our newest member, and are excited about the many prospects. Their EDA technology leadership in green, low-power design and design-for-manufacturing solutions will benefit many of our members,” said Horacio Mendez, executive director of the SOI Industry Consortium. “Mentor’s strengths in mixed signal and RF design enablement are also well-aligned with the expanding usage of SOI.”
The SOI Industry Consortium welcomes companies, organizations, government and academic institutions to join the group in applying the full benefits of SOI-based electronics to global sustainability challenges and lowering the total cost-of-ownership of electronics.
About the SOI Industry Consortium:
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing innovation leaders from the entire electronics industry infrastructure, current SOI Industry Consortium members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, GLOBALFOUNDRIES, IBM, IMEC, Infotech, Innovative Silicon, Kanazawa Institute of Technology , KLA-Tencor, Magma Design, Mentor Graphics, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, TSMC, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian. Membership is open to all companies and institutions throughout the electronics industry. For more information, please visit www.soiconsortium.org.
Press Contacts:
Camille Darnaud-Dufour
+33 (0) 6 79 49 51 43
camille.darnaud-dufour@soiconsortium.org
Legal Note:
The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.
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Hot news
PRESENTATION The Revolutionary Scope of Multi-Gate Transistors
[University of California Berkeley]
ARTICLE FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor, Part 1
[ST-Ericsson Technology Blog]
ARTICLE Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
ARTICLE Soitec provides affordable paths to higher performance, lower-power processors for mobile and consumer devices
[Soitec]
PRESENTATION ST-Ericsson announces next-gen NovaThor at 28nm, on FD-SOI
[ST-Ericsson]
ARTICLE ST-Ericsson’s Next-gen NovaThor: This Year, at 28nm, on FD-SOI Wafers from Soitec
[Advanced Substrate News]
ARTICLE Workshop: Fully Depleted SOI - February 24, 2012 - San Francisco, CA - Presentations available
[SOI Industry Consortium]
