SOI Applications
NEW Filter our 316 articles by market or company:
SOI Fundamentals
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
[EDA360 Insider]
Design/IP
Video interview of David Desharnais (Cadence) by Jeff Wolf (SOI Industry Consortium)
[Chipestimate.tv]
Analog/HV/RF
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Photonics
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
Power
A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]
NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications.
[NXP]
Sensors/MEMS
How an SOI MEMS are built : MEMS first™ process
[SiTime]
A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
Last post on February 03, 2012:
STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display
#18 - Fall/Winter 2011/12
SOI on the Roadmaps
- FD-SOI: ST & 28nm SOCs; ARM & design porting
- Apps – NXP automotive sensors, AMD 32nm Bulldozer
- SOI Conference (IBM, Intel, Leti, GloFo, ST, ARM, Peregrine & more)
- SOI Consortium – FD-SOI whitepaper overview & excerpts
Press releases
The SOI Industry Consortium announces first general members' forum
Download this press release
in pdf format
BOSTON, MASS., November 6, 2008 – The SOI Industry Consortium announced today that it will hold the First Annual SOI Industry Consortium Members’ Forum, one year after the organization’s formal launch. The General Member’s Forum will be held at the TechMart in Santa Clara, California on November 11, 2008. The SOI Industry Consortium Forum is designed to further the consortium’s mission of accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. “The consortium is entering its second year with great momentum. We have developed the SOI Industry Consortium Forum to share and discuss members’ research and findings, and to bring the stakeholders of SOI technology together to network and provide inputs on the consortium’s priorities,” said Horacio Mendez, executive director of the SOI Industry Consortium. The program will include a keynote from Nvidia on graphics silicon technology needs and its impact on SOI. Also, as one of the big key challenges in today's products are memory content and memory stability, the program includes two presentations on these issues. Other presenters will review current challenges of the industry and how SOI provides solutions. Topics include: • SOI For Low-Power Applications • Considerations when comparing Bulk and SOI • SOI: Embedded memory challenges and solutions • SOI: Revolutionary Memory Solutions The event will close with a panel entitled "SOI's Future and the Foundry Business: What are the key ingredients for success?". It will include discussions about the design ecosystem, low-power markets and all of the remaining challenges to full SOI deployment in the fabless/foundry arena. This event is open to anyone currently working for a company that is a member of the consortium. The SOI Industry Consortium is open to any company, organization or academic institution with an interest in SOI. Visit the web site, www.soiconsortium.org, for more information on attending the event and/or on joining the consortium. About the SOI Industry Consortium: The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing leaders spanning the entire electronics industry infrastructure, SOI Industry Consortium members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Nvidia, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Symmid Semiconductor, Synopsys, TSMC, Tyndall Institute, UCL (University Catholique of Louvain) and UMC. Membership is open to all companies and institutions throughout the electronics industry. For more information, see www.soiconsortium.org Legal Note: The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions. Press Contact: Camille Darnaud-Dufour +33 (0) 6 79 49 51 43 camille.darnaud-dufour@soiconsortium.org
Share this press release
Hot news
ARTICLE Intel Delays Finfets
[Electronics Weekly]
ARTICLE ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]
ARTICLE White paper: Considerations for Bulk CMOS to FD-SOI Design Porting
[SOI Industry Consortium]
ARTICLE Workshop: Fully Depleted SOI - April 28, 2011 - Hsinchu, Taiwan
[SOI Industry Consortium]
PUBLICATION Planar FD-SOI CMOS: The Competitive Advantage Mobile Silicon Technology
[SOI Industry Consortium]
PRESENTATION Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips
[Horacio Mendez, Executive Director, SOI Industry Consortium]
