NEW Filter our 213 articles by market or company:
• IBM, STM, Hitachi, Leti, Soitec on FD-SOI
• Special supplement: SOI Industry Consortium
• Medical apps: KEK, Hitachi, UCL, Nanosens
• IEEE fellows, Industry Buzz and more


Download this press release
in pdf format
BOSTON, MASS., November 6, 2008 – The SOI Industry Consortium announced today that it will hold the First Annual SOI Industry Consortium Members’ Forum, one year after the organization’s formal launch. The General Member’s Forum will be held at the TechMart in Santa Clara, California on November 11, 2008. The SOI Industry Consortium Forum is designed to further the consortium’s mission of accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption.
“The consortium is entering its second year with great momentum. We have developed the SOI Industry Consortium Forum to share and discuss members’ research and findings, and to bring the stakeholders of SOI technology together to network and provide inputs on the consortium’s priorities,” said Horacio Mendez, executive director of the SOI Industry Consortium.
The program will include a keynote from Nvidia on graphics silicon technology needs and its impact on SOI. Also, as one of the big key challenges in today's products are memory content and memory stability, the program includes two presentations on these issues. Other presenters will review current challenges of the industry and how SOI provides solutions. Topics include:
• SOI For Low-Power Applications
• Considerations when comparing Bulk and SOI
• SOI: Embedded memory challenges and solutions
• SOI: Revolutionary Memory Solutions
The event will close with a panel entitled "SOI's Future and the Foundry Business: What are the key ingredients for success?". It will include discussions about the design ecosystem, low-power markets and all of the remaining challenges to full SOI deployment in the fabless/foundry arena.
This event is open to anyone currently working for a company that is a member of the consortium. The SOI Industry Consortium is open to any company, organization or academic institution with an interest in SOI.
Visit the web site, www.soiconsortium.org, for more information on attending the event and/or on joining the consortium.
About the SOI Industry Consortium:
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing leaders spanning the entire electronics industry infrastructure, SOI Industry Consortium members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Nvidia, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Symmid Semiconductor, Synopsys, TSMC, Tyndall Institute, UCL (University Catholique of Louvain) and UMC. Membership is open to all companies and institutions throughout the electronics industry. For more information, see www.soiconsortium.org
Legal Note: The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.
Press Contact:
Camille Darnaud-Dufour
+33 (0) 6 79 49 51 43
camille.darnaud-dufour@soiconsortium.org
Share this press release
• White paper on Silicon On Insulator (SOI) implementation [Infotech Enterprises Ltd.]
• Roadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic [UC Louvain]
texte [Chipestimate.tv]
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]