SOI Applications

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SOI Fundamentals

Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]

SOI Technology
[ISU Electrical and Computer Engineering Archives]

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Process Technology

SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]

Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]

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Photonics

Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption. [Department of Information Technology (INTEC), Ghent University]

Device engineering for silicon photonics
[NPG Asia Materials]

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Power

A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]

NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications. [NXP]

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Sensors/MEMS

How an SOI MEMS are built : MEMS first™ process
[SiTime]

A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]

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3D integration

Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin [Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]

Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability [EV Group (EVG)]

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Last post on February 03, 2012:

STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display

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#18 - Fall/Winter 2011/12
SOI on the Roadmaps

FD-SOI: ST & 28nm SOCs; ARM & design porting
Apps – NXP automotive sensors, AMD 32nm Bulldozer
SOI Conference (IBM, Intel, Leti, GloFo, ST, ARM, Peregrine & more)
SOI Consortium – FD-SOI whitepaper overview & excerpts

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Press releases

Additional quotes

"ARM designs physical and processor IP at the heart of low-power products across a wide range of applications. SOI technology with ARM IP enables our partners to realize maximum green benefits in their design,” said Simon Segars, EVP and General Manager, Physical IP Division of ARM, "Our IP enables SoC designers to integrate SOI IP into their standard ASIC/COT design flows to help them achieve up to 50% reduction in dynamic power consumption." "As a leader in low power design, Cadence continues to invest heavily in new technologies and methodologies to provide maximum power efficiency, now a key consideration for all designs," said Dr. Chi-Ping Hsu, senior vice president of research and development for the implementation group at Cadence. "We are pleased to announce our end-to-end support for the SOI process within the Cadence Low Power Design Solution, thereby offering customers an integrated and low-risk path to maximizing the potential SOI benefits on their green designs." "The unique characteristics of SOI enables clients to achieve high performance, low power and high density chip designs." said Mark Ireland, vice president, IBM Semiconductor Platforms. "This cutting-edge technology is being adopted in a wide range of applications including systems, networking, storage, gaming and consumer applications. SOI has been an integral part of IBM's system leadership. " “SOI can save 30% and still enable increased performance,”said André-Jacques Auberton-Hervé, Chairman of the SOI Consortium. “For those looking to make a bigger reduction in their power budget, SOI can enabled up to 50% savings in power at a constant performance level. These are motivating figures, especialy when put in the context of high-volume consumer markets.” “For those of us in the SOI community, being “green” has always been an integral part of our agenda,” said Dr. Jocelyne Wasselin, VP Business Development at Soitec. “Whether the primary driver for using SOI is power savings, performance or integration challenges, there is a cascading cost effect enabling effi ciencies at virtually all levels of the value chain.” “Designing today’s low-power chips on SOI substrates with Synopsys’ Eclypse low-power design solution delivers greener designs and systems.” - Kevin Kranen, Director of Strategic Alliances, Synopsys Inc. "UMC has been incorporating the benefits of SOI technology across multiple semiconductor applications such as MEMS, photonics, and our 65nm high-speed process portfolio," said W.Y. Chen, senior vice president of UMC. "The energy efficiency of SOI adds to the attractiveness of the technology and conforms with UMC's green initiative to provide environmentally friendly processes for our customers. We look forward to further developing SOI to provide customers with solutions that enable more innovative applications for a better and greener planet." "SOI is the technology of choice for our R&D on Ultra-Low-Power applications (www.dice.ucl.ac.be/greenelectronics/)," said Prof. Denis Flandre, Université Catholique de Louvain, Belgium. "Optimal and innovative design techniques have indeed helped us demonstrate ultra-low-voltage and ultra-low-leakage SOI circuits with about 10x power improvements, and sometimes even much more."

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