SOI Applications

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SOI Fundamentals

Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]

SOI Technology
[ISU Electrical and Computer Engineering Archives]

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Process Technology

SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]

Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]

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Photonics

Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption. [Department of Information Technology (INTEC), Ghent University]

Device engineering for silicon photonics
[NPG Asia Materials]

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Power

A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]

NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications. [NXP]

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Sensors/MEMS

How an SOI MEMS are built : MEMS first™ process
[SiTime]

A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]

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3D integration

Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin [Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]

Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability [EV Group (EVG)]

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Last post on February 03, 2012:

STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display

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#18 - Fall/Winter 2011/12
SOI on the Roadmaps

FD-SOI: ST & 28nm SOCs; ARM & design porting
Apps – NXP automotive sensors, AMD 32nm Bulldozer
SOI Conference (IBM, Intel, Leti, GloFo, ST, ARM, Peregrine & more)
SOI Consortium – FD-SOI whitepaper overview & excerpts

> Read the full edition

Press releases

SOI Industry Consortium announces SOI Design Clinic at ARM TechCon3

New SOI Design Clinic To Be Held on October 21, 2009 in Santa Clara, California

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in pdf format

Boston, MASS., October 8, 2009 – The SOI Industry Consortium today announced an initiative to deliver a silicon on insulator (SOI) educational event in conjunction with ARM TechCon3 to help the electronics industry reap the benefits of SOI. Responding to the industry’s need for education in this area, the SOI Design Clinic will provide IC designers and engineering management with a technical understanding of significant differences between designing on SOI versus bulk silicon, and how to receive the power-saving, integration, reliability and performance advantages of SOI. Respected experts from the semiconductor industry will deliver training and share their insights at this practical and timely event, to help attendees evaluate and plan their move to SOI.

Shrinking semiconductor feature sizes demonstrate that CMOS on bulk silicon is rapidly reaching its technological limits for many applications. Process complexity, variability, short-channel effects, leakage, power density, and reliability are just a few reasons why technology leaders transition to SOI. Today available foundry processes, libraries, EDA tools and designer training are making SOI accessible to fabless semiconductor companies and OEMs, and enabling first-time SOI design teams to achieve improved power, performance and area results in their customary design cycle times, as documented by ARM in a recent study released today.

The design clinic will take place in the Santa Clara Convention Center (California) on October 21, 2009, co-located with ARM TechCon3. Presented in two 3 hour sessions of live classroom instruction, from 9am to 12noon and from 2pm to 5pm, the program will include lunch, admission to the ARM TechCon3 keynote session and a post-clinic reception on the exhibition floor. The design clinic content will focus on:

SOI fundamentals
Current and emerging bulk CMOS design challenges and how SOI eliminates/ mitigates them
Lower power design techniques
High performance microprocessor system design techniques
PDKs, libraries, IP and EDA tool ecosystem for SOI design
Standard cell/custom design flows and methodologies
Projections for the future of SOI design

Readers can visit http://soidesignclinic.com to review program details and register for the event.

The SOI Industry Consortium welcomes companies, organizations, government and academic institutions to join the group in applying the full benefits of SOI-based electronics to global sustainability challenges and lowering the total cost-of-ownership of electronics. To find out more, to join or to arrange for a company-specific design clinic, please visit www.soiconsortium.org.

About the SOI Industry Consortium
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing innovation leaders from the entire electronics industry infrastructure, current SOI Industry Consortium members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, GLOBALFOUNDRIES, IBM, IMEC, Infotech, Innovative Silicon, Kanazawa Institute of Technology, College of Engineering , KLA-Tencor, Magma Design, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, TSMC, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian. Membership is open to all companies and institutions throughout the electronics industry. For more information, please visit www.soiconsortium.org.

Press Contacts
Camille Darnaud-Dufour
+33 (0) 6 79 49 51 43
camille.darnaud-dufour@soiconsortium.org

Legal Note
The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.

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