SOI Applications

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SOI Fundamentals

Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]

SOI Technology
[ISU Electrical and Computer Engineering Archives]

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Process Technology

SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]

Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]

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Photonics

Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption. [Department of Information Technology (INTEC), Ghent University]

Device engineering for silicon photonics
[NPG Asia Materials]

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Power

A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]

NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications. [NXP]

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Sensors/MEMS

How an SOI MEMS are built : MEMS first™ process
[SiTime]

A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]

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3D integration

Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin [Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]

Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability [EV Group (EVG)]

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Last post on February 03, 2012:

STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display

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#18 - Fall/Winter 2011/12
SOI on the Roadmaps

FD-SOI: ST & 28nm SOCs; ARM & design porting
Apps – NXP automotive sensors, AMD 32nm Bulldozer
SOI Conference (IBM, Intel, Leti, GloFo, ST, ARM, Peregrine & more)
SOI Consortium – FD-SOI whitepaper overview & excerpts

> Read the full edition

Press releases

The SOI Industry Consortium announces results of a SOI and bulk FinFETs comparison study

SOI’s Simpler Process Reduces Variability

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Boston, MASS., October 21, 2009 – The SOI Industry Consortium today announced the results of a silicon-on-insulator (SOI) and bulk FinFETs comparison study conducted by the organization with the support of some of its key members. The study has evaluated performance, process variability, and cost differences between FinFETs fabricated with junction isolation on bulk silicon wafers, and FinFETs fabricated on SOI wafers. The analysis shows that fabrication on bulk and SOI wafers is for all practical purposes equivalent in performance and cost. However, bulk-based FinFETs are much more challenging to manufacture due to increased process variability.

Transistors are the miniscule on/off switches that make up the integrated circuits in today's microprocessors. The Fin Field Effect Transistor (FinFET) design relies upon a thin vertical silicon "fin" to help control leakage of current through the transistor when it is in the "off" stage. This design combination allows for the creation of new chips with enhanced performance and ever-shrinking geometries.

“This is a very important study. As the industry contemplates transitioning to non-planar transistors, it is vital to bring the best technical assessments possible of manufacturability, cost and performance between the two substrate options: bulk and SOI,” comments Horacio Mendez, executive director of the SOI Industry Consortium. “This collaborative effort between companies and R&D institutes takes a careful look at these critical parameters and its impact to end products.”

As the semiconductor industry looks toward the 22nm technology node, some manufacturers are considering a transition from traditional planar CMOS transistors to the three-dimensional FinFET device architecture. Relative to planar transistors, FinFETs offer improved channel control and therefore reduced short channel effects.

SOI simplifies FinFET fabrication: the buried oxide layer acts as an etch-stop and isolates individual transistors; the fin height is a function of the substrate thickness. Process variability comparisons showed that fin height and width are far more easily controlled in the SOI process.

In this study, the fin heights and widths of the FinFET pairs fabricated on bulk were shown to vary between 150 and 160% more than the SOI equivalents. Such variation in these “transistor matching characteristics”, which is the result of complexity in the bulk manufacturing process, can lead to significant end-product variability.

The SOI Industry Consortium welcomes companies, organizations, government and academic institutions to join the group in applying the full benefits of SOI-based electronics to global sustainability challenges and lowering the total cost-of-ownership of electronics. » Download the study

About the SOI Industry Consortium:
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing innovation leaders from the entire electronics industry infrastructure, current SOI Industry Consortium members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, GLOBALFOUNDRIES, IBM, IMEC, Infotech, Innovative Silicon, Kanazawa Institute of Technology , KLA-Tencor, Magma Design, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, TSMC, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian. Membership is open to all companies and institutions throughout the electronics industry. For more information, please visit www.soiconsortium.org.

Press Contacts:
Camille Darnaud-Dufour +33 (0) 6 79 49 51 43 camille.darnaud-dufour@soiconsortium.org

Legal Note
The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.

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