NEW Filter our 214 articles by market or company:
IBM, STM, Hitachi, Leti, Soitec on FD-SOI
Special supplement: SOI Industry Consortium
Medical apps: KEK, Hitachi, UCL, Nanosens
IEEE fellows, Industry Buzz and more

ARM, IBM and Leti Executives Assume BoD Responsibilities

Download this press release
in pdf format
Boston, MA, May 6, 2010 – The SOI Industry Consortium, a not-for-profit organization aimed at accelerating innovation and adoption of energy-efficient silicon-on-insulator (SOI) technology across the electronics industry, today announced new additions to its board of directors: Michael J. Cadigan, general manager, IBM Microelectronics Systems & Technology Group, as the new board chair; Simon Segars, executive vice president and general manager, Physical IP Division, ARM Ltd.; and Laurent Malier, chief executive officer of CEA-Leti, as its new treasurer.
“We are extremely pleased to have Mike, Simon and Laurent join us to help shape the future of our organization and our collaborative efforts to promote and develop SOI’s low power capabilities,”said Horacio Mendez, executive director of the SOI Industry Consortium. “We would like to thank our outgoing chair, André-Jacques Auberton-Hervé for his outstanding leadership in the development of the consortium. Thanks also to Tom Lantzsch, from ARM, who has served us well as treasurer of the board, and to Mark Ireland for his outstanding support representing IBM on our board for the past three years.”
André-Jacques Auberton-Hervé, chief executive officer of Soitec, continues to serve the SOI Industry Consortium as chair emeritus.
Current members of the SOI Industry Consortium board of directors are:
- Michael J. Cadigan, chairman; IBM Microelectronics Systems & Technology Group
- Laurent Malier, treasurer; CEA-Leti
- André-Jacques Auberton-Hervé, chair emeritus; Soitec
- Horacio Mendez; SOI Industry Consortium executive director
- Simon Segars; ARM Ltd.
- Udo Nothelfer; GLOBALFOUNDRIES
- Michael Mendicino; Freescale Semiconductor
- Joel Hartmann; STMicroelectronics
- C.S. Yeh; UMC
The SOI Industry Consortium welcomes companies, organizations, government and academic institutions to join the group in extending Moore’s law scaling and applying the full benefits of SOI-based electronics to global sustainability challenges, lowering the total cost-of-ownership of electronics and improving the quality of life.
About the SOI Industry Consortium:
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Providing a platform for global collaboration throughout the value chain, the SOI Industry Consortium’s membership includes: ARM, BroadPak, Cadence Design Systems, CEA-Léti, Freescale Semiconductor, GLOBALFOUNDRIES, IBM, IMEC, Infotech, Innovative Silicon, Kanazawa Institute of Technology, KLA-Tencor, MEMC, Mentor Graphics, MIT Lincoln Laboratories, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian. Membership is open to all companies and institutions throughout the electronics industry. For more information please visit www.soiconsortium.org.
Press Contacts:
Jeff Wolf
+1 925 454 9171
jeff.wolf@soiconsortium.org
Camille Darnaud-Dufour
+33 (0) 6 79 49 51 43
camille.darnaud-dufour@soiconsortium.org
Legal Note
The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.
Share this press release
White paper on Silicon On Insulator (SOI) implementation [Infotech Enterprises Ltd.]
Roadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic [UC Louvain]
texte [Chipestimate.tv]
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]