SOI CONSORTIUM - FD-SOI SYMPOSIUM - Stanford 2016 FD-SOI and RF-SOI Forum - Tokyo 2016 SureCore Technology White paper 20nm FD SOI logic evaluation model cards available Fully Depleted SOI Corner

SureCore Technology White paper

SureCore technology not driven by Vmin reduction allows to avoid a number of issues with bit cell stability and reduce power consumption dramatically

Read the white paper

20nm FD SOI logic evaluation model cards available

Enabled in cooperation with Accelicon

E-mail us (NDA required)

Fully Depleted SOI Corner

Access to all workshops' presentations, white papers, articles and more!

Visit the corner

SOI Consortium FD-SOI and RF-SOI Forum

On January 21st 2016 leading companies joined the SOI Industry Consortium in Tokyo (Japan)

Read the presentations

SOI Consortium
FD-SOI Symposium

On April 13th 2016 leading companies attended the SOI Consortium FD-SOI Symposium in San Jose, California, USA

Read the first presentations available

Get Connected

To automatically receive by e-mail our latest news, please provide us with the following information. Fields marked with an asterisk (*) are required.