Workshop: "FD SOI architecture, technology platform for Low Power applications for 22nm and beyond", sponsored by the SOI Consortium and IMEC.
October 2009

The development of fully depleted SOI has gained strong momentum in recent years. Although initially FinFETs appeared to be a preferred FDSOI architecture, recent major advances in planar FDSOI devices are strongly positioning this technology towards an interception of the 22/20nm node for Low Power applications. From a design perspective, planar FDSOI is an evolutionary approach that is easier to implement than FinFETs. FDSOI CMOS has proved to reduce the Vt variability by 50-60%, makes possible the smallest SRAM cell operated at Vdd=0.5V with an excellent SNM, reduces Ioff by orders of magnitude and preserves a target performance at a cost per die that is comparable or lower than the equivalent bulk.

Presentations:

• FD-SOI for Low Power CMOS

• Hybrid SOI and Bulk Integration

• Planar FD-SOI technology

• Circuit Design with Planar and Vertical FD-SOI Transistors

• UTSOI and UTBOX wafer readiness

• FD-SOI Technology Benefits for SRAM at the 22nm Node

• Floating Body Cell for Embedded and Standalone DRAM

• Substrate Readiness for ETSOI

• Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications