SOI Technology Summit 2013 Shanghai SureCore Technology White paper 20nm FD SOI logic evaluation model cards available Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips Fully Depleted SOI Corner

SureCore Technology White paper

SureCore technology not driven by Vmin reduction allows to avoid a number of issues with bit cell stability and reduce power consumption dramatically

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20nm FD SOI logic evaluation model cards available

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Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips

By Horacio Mendez, Executive Director

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Fully Depleted SOI Corner

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SOI Technology Summit 2013 - Shanghai, China

The presentations are available online!

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Workshop: SOI Technology Summit 2013 - Shanghai, China

PRESENTATION
Workshop: SOI Technology Summit 2013 - Shanghai, China

Aiming to promote the benefits of SOI technology and reduce the barriers to market adoption, SOI Industry Consortium (a group of leading companies with the mission of accelerating SOI innovation into broad markets), SIMIT (Shanghai Institute of Microsystem and Information Technology, CAS, a pioneer of SOI technology in China), and VeriSilicon Holdings Co., Ltd. hosted “SOI Technology Summit” in Shanghai, China.

Workshop: FD-SOI 2013 - Kyoto, Japan

PRESENTATION
Workshop: FD-SOI 2013 - Kyoto, Japan

Leading member companies from the SOI Industry Consortium conducted a workshop covering planar FD-SOI technologies – ideally suited for highly energy-efficient system-on-chip (SOC) devices – on June 15, 2013 in Kyoto, Japan.

White paper: Surecore technology not driven by Vmin reduction allows to avoid a number of issues with bit cell stability and reduce power consumption dramatically

WHITE PAPER
White paper: Surecore technology not driven by Vmin reduction allows to avoid a number of issues with bit cell stability and reduce power consumption dramatically

This whitepaper has been written to provide an overview of the technology developed by sureCore and a comparison against conventional approaches.

Sheffield firm gets funding to develop low power SRAM for finfet processes

ARTICLE
Sheffield firm gets funding to develop low power SRAM for finfet processes [Electronics Weekly]

White paper: Innovative wafers for energy-efficient CMOS technology

WHITE PAPER
White paper: Innovative wafers for energy-efficient CMOS technology

By Xavier Cauchy, Digital Applications and Strategic Marketing, Soitec

DAC 2012: video interview of Horacio Mendez, Executive Director, SOI Industry Consortium

ARTICLE
DAC 2012: video interview of Horacio Mendez, Executive Director, SOI Industry Consortium [EDACafe.com]