White papers

White paper: Surecore technology not driven by Vmin reduction allows to avoid a number of issues with bit cell stability and reduce power consumption dramatically
This whitepaper has been written to provide an overview of the technology developed by sureCore and a comparison against conventional approaches.

White paper: Innovative wafers for energy-efficient CMOS technology
By Xavier Cauchy, Digital Applications and Strategic Marketing, Soitec

White paper: Economic impact of the technology choices at 28nm/20nm
A white paper By Dr. Handel Jones, Founder and CEO of IBS, Inc. (Los Gatos, California)

White paper: Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond
This document considers the challenges to obtain competitive silicon technology for the upcoming generation of System-On-Chip ICs. It suggests planar fully depleted technology deserves serious interest. After outlining some implementation choices, a number of circuit-level benchmark results as well as some important design aspects are presented. It is found that this technology combines high performance, power efficiency and cost-effectiveness, which makes it a very attractive candidate to serve the needs of mobile and consumer multimedia SOCs starting at the 28nm node and scalable down to 14nm.
[STMicroelectronics, Soitec]

White paper: Considerations for Bulk CMOS to FD-SOI Design Porting
The scope of this study is to examine the efforts required for a straight “port” of an existing bulk CMOS design to FD-SOI at the same node. The objective would be to get value from FD-SOI for a modest redesign effort – even if this means not necessarily taking maximum advantage of the potentialities of FD-SOI. The focus is on FD-SOI with Ultra-Thin Buried Oxide. This document intends to be sufficiently generic to be applicable to different possible implementations of the FD-SOI technology by foundries.
[SOI Industry Consortium]

White paper: Fully Depleted SOI - Designed for low power
FULLY DEPLETED SOI is a CMOS silicon technology specifically designed to operate at very low power while maximizing performance, manufacturability and reducing the overall cost.
[Horacio Mendez, Executive Director, SOI Industry Consortium]

White paper: Forecasted impact of FD SOI technology on design
As potential users of Fully Depleted Silicon-on-Insulator (FD-SOI) technology for the 22nm/20nm CMOS node and beyond realize its many interests, the question of its impact on design practices arises. Although FD-SOI for next generation technology nodes is not on commercial offer yet, it is nevertheless important to bring early answers or indications to that question. This document therefore proposes a synthesis of what is known or can be reasonably expected from FD-SOI from a design perspective, and indicates some interesting new potentialities that designers may be able to exploit.
[By Xavier CAUCHY, Digital Application Manager, Soitec]

White paper: Questions and answers on FD SOI technology
This document is a high level introduction to FD-SOI technology and its applicability to next technology nodes, in the form of a few key questions and their quick answers. No deep technical details are provided here, however Question 15 provides some relevant links. Short answers are provided first (hypertext links are provided, just click on the question of interest), followed by slightly more detailed answers for the interested readers.
[By Xavier CAUCHY, Digital Applications Manager, Soitec, with François ANDRIEU, Senior Research Engineer, LETI]

White paper on Silicon On Insulator (SOI) implementation
by Narayana Murty Kodeti
[Infotech Enterprises Ltd.]