SOI Applications
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Updated: June 6, 2013
SOI Fundamentals
Bulk vs SOI FinFET
[SOI Industry Consortium]
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
Sheffield firm gets funding to develop low power SRAM for finfet processes
[Electronics Weekly]
Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
Design/IP
GlobalFoundries to Fab 28/20nm FD-SOI Chips for ST; ST Technology Open to Other GF Customers
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Analog/HV/RF
High Voltage and High Reliability Silicon-on-Insulator Power IC Technologies and Their Application to 750 V 4.5 A Micro-Inverter IC
[Japanese Journal of Applied Physics 51 (2012)]
Smart power saves power
ST’s newest SOI-based smart power technology delivers big reductions in power consumption in medical equipment, hybrid-electric-vehicle chargers and more.
[Advanced Substrate News]
Photonics
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
Photonics on the Move
SOI is at the heart of silicon photonics. Here’s an overview of past, present and future trends.
[Advanced Substrate News]
Power
NovaThor SmartPhone Chip on 28nm FD-SOI: ST-Ericsson Blogger Tells All; PC Mag Sees Light
[Advanced Substrate News]
Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Sensors/MEMS
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News]
Imec and Genalyte have successfully developed and produced a set of disposable SOI-photonics biosensor chips for Genalyte’s diagnostic and molecular detection equipment
[Advanced Substrate News]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
American Semiconductor has announced the FleX-MCUâ„¢ product family.
#20 – Fall/Winter 2012/13
The Move to Fully-Depleted: Manufacturing, Economics, Design
- FD-SOI: ST/Chery interview; CMP's MPW runs; IBS on cost-savings
- FD & wafers: SEH & Soitec
- IBM's Fin-on-Oxide/FinFET
- SOI Consortium – FD-SOI & wafer capacity for mobile
Why SOI, why now?
Silicon-on-insulator (SOI) technology electrically insulates a fine layer of the monocrystalline silicon from the rest of the silicon wafer. This opens up new avenues for innovation, delivering performance, power and area (PPA) advantages that bulk CMOS technologies cannot easily match.
And, the SOI manufacturing process is actually simpler than bulk-based CMOS processes. In bulk, isolation and other processes continue to grow in complexity – and cost – with scaling. Recent studies indicate that overall SOI solutions can be cost-neutral – or even cheaper than bulk silicon.
2008 SOI Survey Analysis
SOI technology: Semiconductor perception & awareness study, by Global Semiconductor Alliance (GSA) in collaboration with the SOI Industry Consortium.
SOI Cost of Ownership
"From a manufacturing point of view, if you consider the cost of a completed, packaged IC, Semico's analysis found that SOI adds only 4 to 6% to the total manufacturing cost. If you add design optimization of the digital logic, SOI cost of ownership (COO) is cut by another 10%. At 65nm, with basic design optimization of the digital logic, SOI is often cheaper than bulk."
Joanne Itow,
Semiconductor Partners, LLC 2007
The impact of SOI on manufacturing costs with respect to die area, technology node and number of mask layers, at the processed wafer level, assuming basic design optimization of the digital logic.*
Source: Semico Research 2006
* This is an all digital logic scenario, which includes typical design optimization of the digital logic. It does not include additional cost reductions that could be realized through memory design optimization.
Hot news
ARTICLE Sheffield firm gets funding to develop low power SRAM for finfet processes
[Electronics Weekly]
PRESENTATION Forum: FD-SOI Technology - April 22nd, 2013 - Hsinchu, Taiwan
[SOI Industry Consortium]
PRESENTATION Symposium: Fully Depleted Transistors Technology - December 10, 2012 – San Francisco, CA
[SOI Industry Consortium]
WHITE PAPER White paper: Innovative wafers for energy-efficient CMOS technology
ARTICLE DAC 2012: video interview of Horacio Mendez, Executive Director, SOI Industry Consortium
[EDACafe.com]
