Silicon-on-insulator (SOI) technology electrically insulates a fine layer of the monocrystalline silicon from the rest of the silicon wafer. This opens up new avenues for innovation, delivering performance, power and area (PPA) advantages that bulk CMOS technologies cannot easily match.

And, the SOI manufacturing process is actually simpler than bulk-based CMOS processes. In bulk, isolation and other processes continue to grow in complexity – and cost – with scaling. Recent studies indicate that overall SOI solutions can be cost-neutral – or even cheaper than bulk silicon.

From a manufacturing point of view, if you consider the cost of a completed, packaged IC, Semico–s analysis found that SOI adds only 4 to 6% to the total manufacturing cost. If you add design optimization of the digital logic, SOI cost of ownership (COO) is cut by another 10%. At 65nm, with basic design optimization of the digital logic, SOI is often cheaper than bulk.

Joanne Itow,
Semiconductor Partners, LLC 2007

SOI Cost of Ownership

The impact of SOI on manufacturing costs with respect to die area, technology node and number of mask layers, at the processed wafer level, assuming basic design optimization of the digital logic.*

Source: Semico Research 2006

* This is an all digital logic scenario, which includes typical design optimization of the digital logic. It does not include additional cost reductions that could be realized through memory design optimization.