SOI Applications

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SOI Fundamentals

Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]

SOI Technology
[ISU Electrical and Computer Engineering Archives]

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Process Technology

SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]

Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]

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Photonics

Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption. [Department of Information Technology (INTEC), Ghent University]

Device engineering for silicon photonics
[NPG Asia Materials]

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Power

A new integrated SOI power device based on self-isolation technology
[State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China]

NXP has launched the UBA2024 and UBA2024A integrated half-bridge power ICs, based on the company’s EZ-HV SOI technology
They enable the easy design of low-cost, very compact, high-reliability, long-life florescent lamp (CFL) applications. [NXP]

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Sensors/MEMS

How an SOI MEMS are built : MEMS first™ process
[SiTime]

A 12GHz bulk-micromachined RF-MEMS phase shifter by SOI layer-separation design
[IEICE Electronics Express]

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3D integration

Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin [Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]

Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability [EV Group (EVG)]

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Last post on February 03, 2012:

STMicroelectronics predicts its new SOI-based STOD13AS power chip could be used in nearly every new smartphone or small electronic device that has an AMOLED display

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#18 - Fall/Winter 2011/12
SOI on the Roadmaps

FD-SOI: ST & 28nm SOCs; ARM & design porting
Apps – NXP automotive sensors, AMD 32nm Bulldozer
SOI Conference (IBM, Intel, Leti, GloFo, ST, ARM, Peregrine & more)
SOI Consortium – FD-SOI whitepaper overview & excerpts

> Read the full edition

Why SOI, why now?

Silicon-on-insulator (SOI) technology electrically insulates a fine layer of the monocrystalline silicon from the rest of the silicon wafer. This opens up new avenues for innovation, delivering performance, power and area (PPA) advantages that bulk CMOS technologies cannot easily match.

And, the SOI manufacturing process is actually simpler than bulk-based CMOS processes. In bulk, isolation and other processes continue to grow in complexity – and cost – with scaling. Recent studies indicate that overall SOI solutions can be cost-neutral – or even cheaper than bulk silicon.

2008 SOI Survey Analysis

SOI technology: Semiconductor perception & awareness study, by Global Semiconductor Alliance (GSA) in collaboration with the SOI Industry Consortium.

» Download the survey

SOI Cost of Ownership

"From a manufacturing point of view, if you consider the cost of a completed, packaged IC, Semico's analysis found that SOI adds only 4 to 6% to the total manufacturing cost. If you add design optimization of the digital logic, SOI cost of ownership (COO) is cut by another 10%. At 65nm, with basic design optimization of the digital logic, SOI is often cheaper than bulk."

Joanne Itow,
Semiconductor Partners, LLC 2007

The impact of SOI on manufacturing costs with respect to die area, technology node and number of mask layers, at the processed wafer level, assuming basic design optimization of the digital logic.*

Source: Semico Research 2006

* This is an all digital logic scenario, which includes typical design optimization of the digital logic. It does not include additional cost reductions that could be realized through memory design optimization.