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Fully Depleted SOI

Workshops' presentations

Apr. 28, 2011Workshop: Fully Depleted SOI - April 28, 2011 - Hsinchu, Taiwan
The SOI Industry Consortium, CEA-Leti and Soitec organized the 5th edition of the FDSOI Workshop at the Ambassador Hotel, in Hsinchu, Taiwan on April 28 following the VLSI-TSA and VLSI-DAT conferences (April 25-27, 2011).
[SOI Industry Consortium]

Dec. 8, 2010Workshop: Fully Depleted SOI - Dec. 8, 2010 - San Francisco, USA
The SOI Consortium, the CEA-Leti and Soitec are organizing an evening workshop at Hilton San Francisco Hotel (333 O'Farrell St) on Wednesday the 8th of December 2010 following the IEDM Conference, focusing on the low power and high speed technology requirements for SOC applications, on design infrastructure and on the advantages for scaling.
[SOI Industry Consortium]

Sep. 25, 2010Workshop: Fully Depleted SOI - Sept. 25, 2010 - Tokyo, Japan
The University of Tokyo, the SOI Consortium, and Soitec organized a one day workshop at the Komaba Research Campus of the University of Tokyo on Saturday the 25th of September 2010 following the SSDM Conference focusing on the FDSOI ecosystem readiness.
[SOI Industry Consortium]

Dec. 31, 2009Workshop: Fully Depleted SOI - Dec. 9, 2009 - Baltimore, USA
Sponsored by Soitec and the SOI Consortium. Experts from around the world gather in Baltimore in December 2009 for a very lively debate on the progress and merits of Fully Depleted SOI.
[SOI Industry Consortium]

Oct. 31, 2009Workshop: FD SOI architecture, technology platform for Low Power applications for 22nm and beyond - Oct. 16, 2009 - Leuven, Belgium
The development of fully depleted SOI has gained strong momentum in recent years. Although initially FinFETs appeared to be a preferred FDSOI architecture, recent major advances in planar FDSOI devices are strongly positioning this technology towards an interception of the 22/20nm node for Low Power applications. From a design perspective, planar FDSOI is an evolutionary approach that is easier to implement than FinFETs. FDSOI CMOS has proved to reduce the Vt variability by 50-60%, makes possible the smallest SRAM cell operated at Vdd=0.5V with an excellent SNM, reduces Ioff by orders of magnitude and preserves a target performance at a cost per die that is comparable or lower than the equivalent bulk.
[SOI Industry Consortium]

White papers

Sep. 6, 2011White paper: Considerations for Bulk CMOS to FD-SOI Design Porting
The scope of this study is to examine the efforts required for a straight “port” of an existing bulk CMOS design to FD-SOI at the same node. The objective would be to get value from FD-SOI for a modest redesign effort – even if this means not necessarily taking maximum advantage of the potentialities of FD-SOI. The focus is on FD-SOI with Ultra-Thin Buried Oxide. This document intends to be sufficiently generic to be applicable to different possible implementations of the FD-SOI technology by foundries.
[SOI Industry Consortium]

Feb. 14, 2011White paper: Fully Depleted SOI - Designed for low power
FULLY DEPLETED SOI is a CMOS silicon technology specifically designed to operate at very low power while maximizing performance, manufacturability and reducing the overall cost.
[Horacio Mendez, Executive Director, SOI Industry Consortium]

Apr. 30, 2010White paper: Forecasted impact of FD SOI technology on design
As potential users of Fully Depleted Silicon-on-Insulator (FD-SOI) technology for the 22nm/20nm CMOS node and beyond realize its many interests, the question of its impact on design practices arises. Although FD-SOI for next generation technology nodes is not on commercial offer yet, it is nevertheless important to bring early answers or indications to that question. This document therefore proposes a synthesis of what is known or can be reasonably expected from FD-SOI from a design perspective, and indicates some interesting new potentialities that designers may be able to exploit.
[By Xavier CAUCHY, Digital Application Manager, Soitec]

Apr. 30, 2010White paper: Questions and answers on FD SOI technology
This document is a high level introduction to FD-SOI technology and its applicability to next technology nodes, in the form of a few key questions and their quick answers. No deep technical details are provided here, however Question 15 provides some relevant links. Short answers are provided first (hypertext links are provided, just click on the question of interest), followed by slightly more detailed answers for the interested readers.
[By Xavier CAUCHY, Digital Applications Manager, Soitec, with François ANDRIEU, Senior Research Engineer, LETI]

Articles, publications, books and short courses

Dec. 6, 2011ST: FD-SOI for Competitive SOCs at 28nm and Beyond
[Advanced Substrate News]

Nov. 7, 2011Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
[EDA360 Insider]

Mar. 30, 2011Performance Evaluation of FD-SOI Mosfets for Different Metal Gate Work Function
[International Journal of VLSI Design & Communication Systems (VLSICS), Vol. 2, No. 1 ]

Mar. 13, 2011Reliability Evaluation of Fully Depleted SOI (FDSOI) Technology for Space Applications
[A. K. Sharma (NASA/GSFC) and A. Teverovsky (QSS Group, Inc.)]

Feb. 24, 2011Planar FD-SOI CMOS: The Competitive Advantage Mobile Silicon Technology
Only Planar Fully-Depleted SOI CMOS Technology will enable the optimal Power-Performance-Area-Cost and Time-to-Market balance you need for your next generation Mobile Product development.
[SOI Industry Consortium]

Feb. 15, 2011FD-SOI Technology Promises Power Advantages for Next-Generation Apps
[Mobile Dev & Design]

Feb. 15, 2011Evaluation of Fully-Depleted SOI for next generation Mobile Consumer Chips
[Horacio Mendez, Executive Director, SOI Industry Consortium]

Feb. 3, 2011MEMC SOI Capability and Fully Depleted SOI Readiness
[MEMC]

Dec. 30, 2010Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate
Components Research, Logic Technology Development, Intel Corporation
[Intel]

Dec. 27, 2010Planar fully depleted SOI: the technological solution against variability
It is well known that the planar fully depleted silicon-on-insulator (SOI) (FDSOI) architecture is a technological booster of the CMOS performance, thanks to better electrostatics than devices on bulk. This article shows that it also greatly improves the variability of the electrical characteristics, thanks to an undoped channel. This leads to good matching performance.
[Solid State Technology]

Dec. 14, 2010Will Future Transistors Appear in Glorious 3D?
[The Applied Materials Blog]

Nov. 1, 2010Short course: Subthreshold-Operation FDSOI. Transistors for Ultralow-Power Electronics
[S. A. Vitale, 2010 IEEE International SOI Conference]

Oct. 10, 2010Fully Depleted SOI for evolutionary planar device scaling
by Carlos Mazure and Christophe Maleville, Soitec
[Soitec]

Jul. 21, 2010FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics
Silicon-on-insulator devices designed for optimum operation at 0.3 V promise longer operational life than conventional application-specific integrated circuits.
[By Steven A. Vitale, Peter W. Wyatt, Member IEEE, Nisha Checka, Jakub Kedzierski, and Craig L. Keast]

Jan. 1, 2006Book: Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications
31 of Japan's leading FD-SOI experts explain design for ultra-low-power applications. Leading experts expect the next-generation of device technology for ultra-low-power applications to be based on FD (fully-depleted) SOI MOSFETs. For circuit designers and university students who would like to learn about FD-SOI design, and get a basic understanding of the material technology and device physics, 31 experts from Japan have written a new textbook. It provides examples of unique circuit designs for ultra-low-power applications, as well as a brief history of SOI material technology and the basic operational mechanism of FD-SOI MOSFETs.
[by Sakurai, Takayasu, Matsuzawa, Akira, Douseki, Takakuni, 2006, XV, 411 p., Hardcover, ISBN: 978-0-387-29217-5]

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