SOI Applications
NEW Filter our 330 articles by market or company:
Updated: April 30, 2012
SOI Fundamentals
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
Design/IP
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
Analog/HV/RF
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Photonics
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
Power
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
Sensors/MEMS
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News ]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
Consortium Website – What’s New
#19 – Spring/Summer 2012
Special Edition: FD-SOI Industrialization
- Technology: ST/Soitec white paper excerpts
- Apps – ST-Ericsson's NovaThor at 28nm (interview)
- 20nm & Beyond: Chenming Hu; Leti
- Wafers: Soitec's Roadmap
- SOI Consortium – benchmarking
Press releases
NVIDIA joins the SOI Industry Consortium
Download this press release
in pdf format
SEMICON WEST, San Francisco, CA, July 16th, 2008 – The SOI Industry Consortium announced today that NVIDIA (Nasdaq: NVDA), the world leader in visual computing technologies, has joined the organization. The SOI Industry Consortium, which was formed in October 2007 by a group of leading companies from across the electronics industry, is aimed at accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. NVIDIA serves the entertainment and consumer market, the professional design and visualization market, as well as the high-performance computing market. Their products are transforming visually-rich and computationally-intensive applications such as video games, film production, broadcasting, industrial design, financial modeling, space exploration, and medical imaging. NVIDIA brings the SOI Consortium membership to twenty three companies. Other members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Synopsys, TSMC, Tyndall Institute, UCL and UMC. “NVIDIA is pleased to join the SOI consortium. We are looking forward in participating on the advancement of such an innovative technology and its applications to future products," said John Chen, VP, Technology and Foundry Operations at NVIDIA. “We are honored to partner with NVIDIA. Their unique insight and perspectives as the world leader in visual computing will be very valuable in articulating the technology direction of the consortium,” says Horacio Mendez, executive director of the SOI Industry Consortium. “NVIDIA’ s entry into the SOI Industry Consortium supports the momentum we are gaining throughout the electronics industry from end-users and enablers to suppliers and manufacturers,” added Mendez. The SOI Industry Consortium is open to any company, organization or academic institution with an interest in SOI. Visit the SOI Industry Consortium in San Francisco, at Semicon West, West Hall, level 2 booth #L12. About the SOI Industry Consortium: The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing leaders spanning the entire electronics industry infrastructure, SOI Industry Consortium members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing Ltd, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Synopsys, TSMC, Tyndall Institute, UCL and UMC. Membership is open to all companies and institutions throughout the electronics industry. Legal note The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions. Press Contact: (also at Semicon West for interviews at the show) Camille Darnaud-Dufour Phone: +33 (0) 6 9 49 51 43 Email : camille.darnaud-dufour@soiconsortium.org
Share this press release
Hot news
PRESENTATION The Revolutionary Scope of Multi-Gate Transistors
[University of California Berkeley]
ARTICLE FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor, Part 1
[ST-Ericsson Technology Blog]
ARTICLE Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
ARTICLE Soitec provides affordable paths to higher performance, lower-power processors for mobile and consumer devices
[Soitec]
PRESENTATION ST-Ericsson announces next-gen NovaThor at 28nm, on FD-SOI
[ST-Ericsson]
ARTICLE ST-Ericsson’s Next-gen NovaThor: This Year, at 28nm, on FD-SOI Wafers from Soitec
[Advanced Substrate News]
ARTICLE Workshop: Fully Depleted SOI - February 24, 2012 - San Francisco, CA - Presentations available
[SOI Industry Consortium]
