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Results from leading semiconductor companies demonstrate the advantages of planar FD-SOI technology over bulk-silicon CMOS

New findings also confirm that planar FD-SOI can match the power and performance of FinFET technology as early as the 28nm node

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Boston, MA, December 8, 2011 – Planar semiconductor devices fabricated on fully depleted silicon-on-insulator (FD-SOI) substrates can deliver significant power and performance advantages over CMOS devices built on bulk-silicon substrates – and can even bring the performance promised by FinFET devices as soon as the 28nm and 20nm technology nodes, according to a collaborative research program recently completed by STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES and other leading semiconductor companies. The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models’ reliability.

New silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers demonstrated that, compared to bulk-silicon CMOS technology, FD-SOI technology presents several advantages in manufacturing next-generation semiconductors, including:

  • Peak performance comparable with the much more leaky ‘General Purpose’ technology flavors, at better dynamic power, and dramatically better leakage power, even lower than what ‘Low Power’ technology flavors achieve;
  • Much better performance than bulk CMOS when the power supply (Vdd) is lowered. At 0.6 volt, critical paths on 28nm FD-SOI circuits were more than 50 percent as fast as the General Purpose technology and more than twice as fast as Low Power technology;
  • The opportunity for substantial power savings of up to 40 percent by using a lower Vdd to reach the same target frequency;
  • The feasibility of running all digital device designs, including SRAMs, at very low Vdd (e.g., 0.6 volt).

In addition, new benchmark simulations at the 20nm node confirmed these trends. When comparing FD-SOI technology to bulk technology specifically intended for System-on-Chip (SOC):

  • Peak performance was improved by 12 to 30 percent at constant total power, depending on design optimization efforts,
  • Low-Vdd (0.7V) performance was improved by 65 to percent,
  • Total power was reduced by 22 to 40 percent at constant maximum operating frequency.

“Not only do the benchmarking results show that FD-SOI can deliver the power and performance of FinFET as early as the 28nm and 20nm technology nodes, but FD-SOI’s ability to accommodate planar architectures presents much lower manufacturing risk than FinFET,” said Horacio Mendez, executive director of the SOI Industry Consortium. “This makes FD-SOI an easy-to-implement solution for cost-sensitive applications that require high performance and low power consumption in standby and active modes, including mobile electronics such as smart phones and tablet computers.”

FD-SOI combines the benefits of a fully depleted silicon technology – which enables fast data processing while using a low-voltage power supply – with planar semiconductor architecture. Planar FD-SOI devices use proven, well-understood design and manufacturing techniques whereas the FinFET approach requires the formation of 3D device structures to fabricate fully depleted transistors. Existing planar bulk CMOS designs can be migrated in a comparatively straightforward way to FD-SOI technology, producing chips that benefit from the intrinsic advantages of fully depleted wafer technology. FD-SOI is also compatible with all power-reduction techniques used by IC designers – and can even boost the efficiency of some. Furthermore, FD-SOI can accommodate some design tweaks that are not available with FinFET designs, such as leveraging dynamic back-bias to increase performance or reduce leakage power in some applications.

In addition to FD-SOI’s power and performance advantages, a study by IC Knowledge published in July 2011 showed that the cost of fabricating 20nm SOC devices on FD-SOI wafers will be comparable to using planar bulk transistors – and more economical than using FinFET.


About the SOI Industry Consortium
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing innovation leaders from the entire electronics industry infrastructure, current SOI Industry Consortium members include AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Freescale Semonductor, GLOBALFOUNDRIES, IBM, IMEC, Infotech, Innovative Silicon, Kanazawa Institute of Technology , KLA-Tencor, MEMC, Mentor Graphics, MIT Lincoln Laboratories, Nvidia, Ritsumeikan University, Samsung, Semico, SEH Europe, Soitec, Stanford University, STMicroelectronics, Synopsys, Tyndall Institute, University of California-Berkeley, University Catholique de Louvain, UMC and Varian. Membership is open to all companies and institutions throughout the electronics industry. For more information, please visit


Press Contact
Camille Darnaud-Dufour
+33 (0) 6 79 49 51 43


Legal Note
The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.

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