SOI Applications
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Updated: April 30, 2012
SOI Fundamentals
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
Process Technology
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Fully Depleted SOI
Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
Design/IP
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
Analog/HV/RF
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Photonics
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
Power
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
Sensors/MEMS
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News ]
3D integration
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]
Consortium Website – What’s New
#19 – Spring/Summer 2012
Special Edition: FD-SOI Industrialization
- Technology: ST/Soitec white paper excerpts
- Apps – ST-Ericsson's NovaThor at 28nm (interview)
- 20nm & Beyond: Chenming Hu; Leti
- Wafers: Soitec's Roadmap
- SOI Consortium – benchmarking
Press releases
SOI Industry Consortium announces first board of directors’ election results
New Executive Director, Horacio Mendez, Also Named
Download this press release
in pdf format
BOSTON, MASS., January 15, 2008 – The SOI Industry Consortium, aimed at accelerating silicon-on-insulator (SOI) innovation into broad markets, announced today its first board of directors’ election results. At the same time the board named Horacio Mendez as the executive director of the newly formed organization.
Horacio Mendez has over 20 years of experience in the semiconductor industry. He was most recently the Director of New Product Development at Freescale Semiconductor where he was responsible for integrating SOI process technology and product design into solutions for the networking and computing microprocessor markets. He has driven the adoption and commercialization of multiple generations of products based on SOI technologies, while working closely with major OEMs.
In his role as the executive director, Mendez will manage the daily operations of the SOI Industry Consortium, ensuring the organization is focused on its vision, goals and commitment to deliver value to its members and the industry.
Technology leaders with a broad depth of industry experience and expertise comprise the SOI Industry Consortium Board of Directors. Working together with the Chair, the Treasurer and the Director, they will manage the strategic decisions of the Consortium, determine the broad lines of the organization’s activities and monitor implementation.
The SOI Industry Consortium Board consists of nine directors elected annually by the voting members. For the first year, the Chair and the Treasurer were elected by a majority of the Charter members prior to the consortium’s official launch on October 8, 2007.
The newly elected Board of Directors announced today includes:
• Udo Nothelfer, AMD (VP Fab 36)
• Tom Lantzch, ARM (VP Marketing PIPD Division; and Consortium Treasurer)
• Kevin Meyer, Chartered Semiconductor Manufacturing Ltd (VP Industry Marketing & Platform Alliances)
• Dirk Wristers, Freescale Semiconductor (Director, Process Technology R&D)
• Mark Ireland, IBM (VP Common Platform)
• André-Jacques Auberton-Hervé, Soitec (CEO and President; and Consortium Chair)
• Joel Hartmann, STMicroelectronics (Crolles2 Alliance Director)
• Ken Weng, TSMC (Deputy Director of SOI Design)
• Shieh-Wei Sun, UMC (COO)
About the SOI Industry Consortium:
The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing leaders spanning the entire electronics industry infrastructure, SOI Industry Consortium charter members include: AMD, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing Ltd, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, NXP, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Synopsys, TSMC and UMC. Membership is open to all companies and institutions throughout the electronics industry.
Safe Harbor:
The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions.
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Hot news
PRESENTATION The Revolutionary Scope of Multi-Gate Transistors
[University of California Berkeley]
ARTICLE FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor, Part 1
[ST-Ericsson Technology Blog]
ARTICLE Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
ARTICLE Soitec provides affordable paths to higher performance, lower-power processors for mobile and consumer devices
[Soitec]
PRESENTATION ST-Ericsson announces next-gen NovaThor at 28nm, on FD-SOI
[ST-Ericsson]
ARTICLE ST-Ericsson’s Next-gen NovaThor: This Year, at 28nm, on FD-SOI Wafers from Soitec
[Advanced Substrate News]
ARTICLE Workshop: Fully Depleted SOI - February 24, 2012 - San Francisco, CA - Presentations available
[SOI Industry Consortium]
