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Updated: April 30, 2012
Chris Edwards explores the 'tricks' semiconductor device manufacturers are using to cope with shrinking feature sizes
[New Electronics]
SOI Technology
[ISU Electrical and Computer Engineering Archives]
SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Hot carrier injection from nanometer-thick silicon-on-insulator films measured by optical second-harmonic generation
[Applied Physics Letters, Vol. 96, Issue 24]
Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
Peregrine's New SP5T RF Switch Offers High Isolation for Infrastructure Apps
[Consumer Electronics Net]
RF Micro Devices(R) Introduces First Silicon Switches for 3G Smartphones and Other High Performance Applications
[RF Micro Devices]
Ultra-high Speed, All-optical Wavelength Converters Using Single SOA and SOI Photonic Integrated Circuits
We report a new family of ultra-fast all-optical wavelength converters. The device architecture employs a single SOA and filtering elements integrated in silicon-on-insulator substrates. These schemes enable high-integration density and low power consumption.
[Department of Information Technology (INTEC), Ghent University]
Device engineering for silicon photonics
[NPG Asia Materials]
NEW Leti: Adding Strain to FD-SOI for 20nm and Beyond
[Advanced Substrate News]
Interview With ST-Ericsson's Chief Chip Architect: SOCs on 28nm FD-SOI – When, Why and How
ST-Ericsson's Chief Chip Architect Louis Tannyeres talks with ASN about the move to 28nm FD-SOI for smartphones and tablet SOCs.
[Advanced Substrate News]
SiTime: Using SOI Technology to Develop High-Performance MEMS Timing Solutions
A radical SOI-based approach puts SiTime at the top of the fast-growing silicon-based timing market.
[Advanced Substrate News ]
Wireless Interconnects for Inter-tier Communication on 3D ICs
By Ankit More and Baris Taskin
[Department of Electrical and Computer Engineering, Drexel University 3141 Chestnut Street, Philadelphia, Pennsylvania 19104, USA]
Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]

Consortium Website – What’s New
#19 – Spring/Summer 2012
Special Edition: FD-SOI Industrialization
Symmid Semiconductor and partners see SOI technology as key to low-power solutions in 45nm and smaller geometries.

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BOSTON, MASS., July 31, 2008 – The SOI Industry Consortium announced today that Symmid Semiconductor Technology (SST), based in Silicon Valley, California, a provider of ASIC design services and intellectual property (IP) porting, has joined the organization as a technical member. With the addition of SST, the SOI Industry Consortium now comprises 24 leading companies from across the electronics industry covering a spectrum of users, enablers, suppliers and manufacturers. This new addition complements the IP focus of the SOI Industry Consortium. SST, which is a technology partner for leading foundries, focuses primarily on system-on-chips (SoCs) with the most stringent performance, power and area requirements. The company is also a design partner of Arrow's Custom Logic Solutions (CLS) Group, one of North America's broadest custom logic solutions providers. “Symmid Semiconductor Technology foresees increased interest in SOI technology for low-power SoC designs. We are excited about our participation in the SOI consortium and we plan to contribute to the momentum of SOI adoption through enablement of IP development and porting,” said Alex Parshad, CEO of Symmid Semiconductor. “We support Symmid Semiconductor's participation in the SOI consortium as we see SOI having an important role in the future of custom logic design,” said Tony Lowry, Director of Engineering at Arrow’s Custom Logic Solutions Group. “Standby power draw is a critical concern to our deep-submicron customers. We view SOI technology as key to low-power solutions in 45nm and smaller geometries.” “We are very happy to have a key IP services provider such as Symmid Semiconductor as part of the SOI consortium, complementing our focus on SOI IP,”said Horacio Mendez, executive director of the SOI Industry Consortium. “The recent GSA survey on SOI technology confirmed that IP availability figures high on the list of perceived gaps in the ecosystem. The addition of Symmid Semiconductor to the Consortium should further strengthen the position of SOI IP for the design community.” The SOI Industry Consortium is open to any company, organization or academic institution with an interest in SOI. The initiative is aimed at accelerating silicon-on-insulator (SOI) adoption in a wide range of markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Current members now include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Nvidia, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Symmid Semiconductor, Synopsys, TSMC, Tyndall Institute, UCL (University Catholique of Louvain) and UMC. About the SOI Industry Consortium: The SOI Industry Consortium is chartered with accelerating silicon-on-insulator (SOI) innovation into broad markets by promoting the benefits of SOI technology and reducing the barriers to adoption. Representing leaders spanning the entire electronics industry infrastructure, SOI Industry Consortium members include: AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Nvidia, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Symmid Semiconductor, Synopsys, TSMC, Tyndall Institute, UCL and UMC. Membership is open to all companies and institutions throughout the electronics industry. Legal Note The views and opinions expressed by the SOI Industry Consortium through officers in the SOI Industry Consortium or in this presentation or other communication vehicles are not necessarily representative of the views and opinions of individual members. Officers of the SOI Industry Consortium speaking on behalf of the Consortium should not be considered to be speaking for the member company or companies they are associated with, but rather as representing the views of the SOI Industry Consortium. Views and opinions are also subject to change without notice, and the SOI Industry Consortium assumes no obligation to update the information in this communication or accompanying discussions. Press Contact: Camille Darnaud-Dufour +33 (0) 6 9 49 51 43 camille.darnaud-dufour@soiconsortium.org
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PRESENTATION The Revolutionary Scope of Multi-Gate Transistors
[University of California Berkeley]
ARTICLE FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor, Part 1
[ST-Ericsson Technology Blog]
ARTICLE Soitec outlines fully depleted product roadmap for advanced planar and three-dimensional transistors
[Soitec]
ARTICLE Soitec provides affordable paths to higher performance, lower-power processors for mobile and consumer devices
[Soitec]
PRESENTATION ST-Ericsson announces next-gen NovaThor at 28nm, on FD-SOI
[ST-Ericsson]
ARTICLE ST-Ericsson’s Next-gen NovaThor: This Year, at 28nm, on FD-SOI Wafers from Soitec
[Advanced Substrate News]
ARTICLE Workshop: Fully Depleted SOI - February 24, 2012 - San Francisco, CA - Presentations available
[SOI Industry Consortium]